1EE 225a: Analog IC Transistor Process Design David W. Parent Associate Professor EE Department SJSU PH: 408.924.3963 EM: [email protected] HP: http://www.engr.sjsu.edu/dparent OH: T 1pm-3pm, F 10:30am-11:30am, ~1:30pm-3:30pm Course Description: Advanced process design, fabrication and testing of transistors for analog integrated circuits, design of statistical process control procedures for yield management, industry standard TCAD tools (Synopsys) and IC fabrication equipment will be used extensively in lab. This is a team-oriented, interdisciplinary course enrolling EE, MatE, ChE, ME, Chemistry and Physics majors. Each student brings a different background to the course. The laboratory is the central theme of the course. This course will require a considerable amount of work outside of regularly scheduled class time so be prepared to invest a lot of time. SPC Overview: This part of the laboratory is intended to demonstrate the basics of Statistical Process Control, for variable and attribute control charting. This includes the statistical background, how to prepare and properly monitor charts, some of the potential pitfalls for chart use, and other topics as time permits. The student will be given to opportunity to perform several analyses to ensure that the concepts presented are maintained. One midterm and one mini-final (for the section) will be given, as announced in class. Students will complete three major team projects: • A design of a 2-mask MOS or solar cell process • SPC project on overlay alignment in a photolithography system. • Fabrication and test of a 2-mask MOS process • Testing MOS-based Analog circuits\ • SPC techniques will be used in each project to explain results and make recommendations. Prerequisites: All students must have had at least a graduate level device physics course such as EE221.2Course Aims: Students should know at the end of this course: 1. CMOS Analog Circuit Design/testing 2. CMOS Processing modeling 3. T-CAD Modeling 4. Metrology 5. Team Work 6. Process Control Outcome Assessment (Grading): There is no curve; the numerical values will directly translate in to a 0 to 4 scale from a 0 to 100 scale. Given that this course is still under development this grading scale is an estimate of what will be assessed. If it is determined that a project can not be completed, due to equipment failures, or some unforeseen problem with lab, then the rest of the points will be evenly distributed over the rest of the projects. Oral and written reports will be assessed on content and proper format. Oral and written reports that are incomplete (for example lacking an abstract or an analysis section) will receive a 0 for the entire report. If it is determined that various teams members are not participating in lab, a lab practical will be given on the various skills required to complete the projects. If a student receives a NO-GO on a supporting skill, then the student’s grade will be lowered by a minimum of 20%. If the non-participation problem continues the team member who is no participating will be re-assigned to another group. If a student misses or is late for a laboratory with out consulting with the team leader or me, the student’s grade will be lowered by 5% on the current project. There are many chances to earn extra credit. Team leaders that excel, or team members that contribute an extra amount can receive up to 5% extra on their final grade. The letter I indicates an individual grade and the letter G indicates a group grade. Individual grades will be moved down if it is shown that a team member is not participating. Surprise quizzes will be administered to test whether or not a student has prepared by reading the material or coordinated with the team members. Failure on a quiz will reduce the student’s grade by 20% for that day’s activities. • Homework (18%)3• Final (15%) • Process Design with TCAD (Sentaurus) (23%): Student teams will o Learn/review the Sentaurus CAD software (I, 3%):  Unix CDS tutorial (I, 2%)  Completing a Tutorial  Modifying a sub-micron MOSFET process file to shift VTO from one specification to another o Design a two MASK NMOS, given a template file (G, 10%). Oral presentation with a poster detailing their design. o Students will write a detailed traveler for their design (G, 10%). • SPC Project (10%): student teams will o Collect and analyze registration overlay error and create a written report with control charts and recommendations for design rules and modifications to the two-mask process designed in the Athena project (G). • Fabrication Project (10%) (G): Students will fabricate and test their two-mask process. They will present their results in a written report. Student will explain their results in terms of their SPC data. • Analog IC Design/Test Project (24%): o Student teams will design/test analog circuits. (G): o Students will fabricate and test their designs and present their work The schedule is a guide!!!!4 # Date Topic 1 1/22/2009 Introduction 2 1/27/2009 Device Physics Review 1 3 1/29/2009 Device Physics Review 2 4 2/3/2009 Design of CMOS Analog Circuits 1 5 2/5/2009 Design of CMOS Analog Circuits 2 6 2/10/2009 4 Mask Process Sequence 7 2/12/2009 Continue With Lab 8 2/17/2009 Design Reviews 9 2/19/2009 Diffusion 10 2/24/2009 Implant 11 2/26/2009 Etching 12 3/3/2009 Design Reviews 13 3/5/2009 Continue With Lab training 14 3/10/2009 SPC 1 15 3/12/2009 SPC 2 16 3/17/2009 Photolithography 17 3/19/2009 Continue with fabrication 18 3/24/2009 Spring Break 19 3/26/2009 Spring Break 20 3/31/2009 Holiday 21 4/2/2009 Continue fabrication project 22 4/7/2009 Testing 1 23 4/9/2009 Continue fabrication project 24 4/14/2009 Testing 2 25 4/16/2009 Continue Testing 26 4/21/2009 Advanced topics 1 27 4/23/2009 Continue Testing 28 4/28/2009 Advanced topics 2 29 4/30/2009 Continue Testing 30 5/5/2009 CMOS Review 31 5/7/2009 Continue Testing 32 5/12/2009 SPC Review 33 5/21/2009 Final Exam 14:45-1700 Textbooks: Required:5R. C. Jaeger, Introduction to Microelectronic Fabrication, 2nd edition, Prentice Hall, 2002, ISBN 0-20144494-1 Additional: • Wolf & R.N. Tauber, Silicon Processing for the VLSI Era: Volume 1- Process Technology, 2nd edition, Lattice Press, 2000. Available at