SJSU EE 225A - Fabrication and Testing of High Gain Transistors (4 pages)

Previewing page 1 of 4 page document View the full content.
View Full Document

Fabrication and Testing of High Gain Transistors



Previewing page 1 of actual document.

View the full content.
View Full Document
View Full Document

Fabrication and Testing of High Gain Transistors

104 views


Pages:
4
School:
San Jose State University
Course:
Ee 225a - Analog Ic Transistor Process Design
Unformatted text preview:

According to the Equation 2 F is a function of the doping Fabrication and Testing of High Gain Transistors Jason Leung Master s Student Toby Ling Master s Student Varun Shah Master s Student Abstract The goal of the project was to understand the fundamentals of analog IC processing by designing and fabricating a high DC gain NMOS transistor High gain instead of high speed is present in the market especially in neuron related applications The authors had the ability to adjust oxidation and well drive times and temperatures to achieve a certain threshold voltage on the transistors The devices were fabricated and tested to confirm functionality Certain values deviated from the expected results showing the importance of testing devices after they are done fabricating Proper evaluation of the wafers needs to be done to ensure a higher yield rate To obtain high DC gain the proposed method was to operate the device in subthreshold region where the GM ID was high The devices were biased to operate in the region and the expected values of the gain were high In the end the devices displayed characteristics of an NMOS transistor yet they need to be biased in such a way to optimize gain I INTRODUCTION T he primary objective of the project was to successfully design a MOS transistor with a practical VT value to be used for high gain analog applications The first stage of the project was to design a simple MIS capacitor to give a quick yet intuitive understanding about how the process works A successful design of the MIS capacitor paved the road to designing the 4 mask NMOS transistor due to their similar characteristics Due to time constraints only a limited number of factors were able to be controlled by the students such as oxidation time and temperature and well drive time and temperature This turned out to be sufficient enough since the goal was to design for a threshold voltage According to the equation 1 V T ms Qi C ox F 0259 ln Where QD Cox NA ni Q D 2 s qN A F C ox ox t ox 2 F 1 2 concentration NA QD and ms are also functions of NA making it an important parameter to control Additionally the Cox term is a function of the tox With NA and tox a large portion of the Equation 1 is covered Hand calculations were closely supported by various TCAD simulations and an oxidation time and temperature was obtained to fabricate a specific tox The NA term is determined by a diffusion process well drive A budget constraint was later introduced which resulted in using only one dose for the well drive step Because of this dose a new VT had to be calculated to maintain practical well drive and temperature times The temperatures and times were put into a 4 mask process traveler and the fabrication was carried out The traveler was followed closely with the proper cleansing and postfurnace testing 2 After the last fabrication step the wafer was tested under a tester to check whether the devices displayed NMOS transistor characteristics A number of other tests were run to test the ability of the devices to function as high gain devices A GM ID biasing technique is employed because a high GM ID value corresponds to an increase in gain 3 It is also known that the maximum GM ID value occurs when a device is in the sub threshold region Therefore the devices were tested and biased to operate in the sub threshold region Under the GM ID biasing technique the equation for the gain of the transistor becomes A V max VM nU T 5 n 1 gI m D max Where 6 UT With 1 V M L 2 B U T ln 3 4 U T kT q 2qN b B V S D Si N b N diff n2 i 7 8 9 n 1 b b with the flat side on the bottom 2 s 10 2qN b Si C ox Next the wafer was tested under a probe tester and the ICS program 5 The first test that was run was the I DS vs VDS curve to make sure that the device is functioning like a transistor 10 The expected results provided by the equations were compared to the measured actual results II EXPERIMENTAL SETUP TCAD simulations that were provided on the EE225A website were used to confirm hand calculations 4 An arbitrary substrate doping was chosen and simulated on the TCAD VT simulation to obtain a tox and VT value Another TCAD MOS CAP simulation was run to determine an oxidation temperature and time to achieve the extracted tox The next step was to determine the diffusion well drive temperature and time to achieve the surface concentration of NA by using the 1 D and 2 D 4 mask process simulation 4 Unfortunately we were limited to only having one standard dose and as a result VT value had to be changed The summarized results are as follows Parameters Initial Values Fig 3 IDS vs VDS graph with device width 75 m and length 65 m VG is swept and the results are plotted The graph clearly shows the regions of operations of a typical transistor cutoff active linear and saturation mode After observing and confirming transistor properties the threshold voltage needed to be found This was achieved by graphing GM vs ID and VG vs ID Final Values Gate Oxide time 48 min 48 min Gate Oxide temp 1000 C 1000 C 14 2 Dose 2 x 10 atoms cm 3 x 1014 atoms cm2 Well Drive time 240 min 120 min Well Drive temp 900 C 900 C Extracted tox 416 5 416 4 Extracted NA 3 379 x 1016 cm3 1 056 x 1017 cm3 Extracted VT 0 394 V 1 32 V Fig 1 A table of values summarizing the TCAD simulations The middle column represents the initial calculated values for the MOS transistor The right column represents the new values that were calculated after the dose Q was set to one value The oxidation time temp and well drive time temp values were inputted into the traveler provided on the EE225A website The steps were followed closely in the fabrication process III RESULTS After completion of the fabrication process the wafers were put under a nanospec to measure the oxide thickness Five points were taken around the wafer and an average thickness was calculated The results are as follows Position Position Position Position Position Average 1 2 3 4 5 424 386 366 392 399 393 4 Fig 2 The positions on the wafer are as follows from 1 5 top center bottom left right These positions are in relation to looking at the wafer Fig 4 GM vs ID upper and VG vs ID lower graph for transistor device with width 75 m and length 65 m Taking the maximum GM value and taking the corresponding VG value a tangent line was drawn on the VG point of the ID vs VG graph and the x intercept gave the VT of the …


View Full Document

Access the best Study Guides, Lecture Notes and Practice Exams

Loading Unlocking...
Login

Join to view Fabrication and Testing of High Gain Transistors and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Fabrication and Testing of High Gain Transistors and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?