I. INTRODUCTIONII. Analytical Equations for Common Source Voltage GainIII. Verification Methodology of Analytical EquationsIV. Gain of Oxide TransistorV. ResultsVI. DiscussionVII. ConclusionAbstract— A design methodology for a common source amplifier to interface with microvolt signal sources such as neural signals is presented. The DC gain of a common source amplifier is correlated with physical properties of a Field Effect Transistor (FET). After process is verified, Gate Oxide transistors were fabricated and tested. A Common Source Amplifier is designed with a measured Voltage Gain of Av = -1146. A comparison of extracted TCAD parameters and actual FET test results was conducted in order to verify entire design process.I. INTRODUCTIONMicrovolt signal levels such as those found in neurons, require a detection circuit with a large gain. The shape of a neuron tends to be of equal width and length, thus causing open gatetransistor used to interface with the neuron to have a transistor width/length ratio of unity that limits the driving capability of transistor. Amplifier gain can be optimized by operating device in moderate inversion. Device s can be biased to perform in moderate inversion by using the gm/ID bias method. With thismethod design parameter can be adjusted in order to achieveelectrical transistor parameters that will result in a common source configuration with optimum gain.II. ANALYTICAL EQUATIONS FOR COMMON SOURCEVOLTAGE GAINUsing circuit design parameters such as common source transistor gain that can be derived from analytical equations that depend on a small set of process variables allows for efficient process and circuit design. Process designers can use this small set of process variable to explore the design space before engaging in time intensive TCAD process simulations. The following equations are presented from the EKV model in [1] and [2]. The DC gain of common source amplifier in weak inversion is given by:AVmax=VMnUT. (1)where VM is the early voltage and is given by VM=L×√2qNb(ΦB+VS . D)εSi. (2) where L is the channel length of the transistor, q represents charge of an electron, Nb is the substrate doping, εSi is the permittivity of silicon, and VS,D is the source or drain to bodyvoltage. ΦB is the built in potential of the source/drain to body diode and is given by: ΦB=UTln(NbNdiffni2). (3) where Ndiff is the sour/drain doping level, and ni is the intrinsic carrier concentration of silicon. UT is the thermodynamic voltage and is given by:UT=kTq(4) where T is temperature in Kelvin and k is the Boltzmann constand (8.617×10-5 eV/K).The slope factor (n) in equation (1) relates ddevice parameters usch as oxide thickness and substrate doping, andsurface potential (ΨS) to the threshold unction, and is given by:n=1+Γb2√Ψs. (5)The slope factor (n) does change with surface potential (ΨS) but can be considered to be constant as long as it is extractedfrom a transistor operating in the region of inversion that is being used for the circuit design.Γb is the substrate modulation factor and is given by:Γb=√2qNbεSiCox. (6)Cox is the gate oxide capacitance due the dielectric and depends on the relative permittivity of the oxide and the thickness of the oxide:Cox=ε0εoxTox. (7) Equations (1) - (7) demonstrate that common source gain can be found in terms of substrate and source/drain doping levels, channel length, oxide thicknesses, silicon and oxide permittivity, intrinsic carrier concentration and temperature.The slope factor (n) can be extracted from a 2-D transistorsimulations or from fabricated transistors. The later can be obtained by relating slope factor (n) to the derivative of the gate voltage (VG) with respect to surface potential (ΨS) of a MOS capacitor as shown in Figure 1.nw=dVGdΨS. (8)High Gain Transistor Design for Microvolt SignalsArturo J. Cisneros, Agus Leonardo, Chihwei Tsao. Spring 2008, SJSUEquation (8) is only valid for weak inversion and can physically be thought of as the gate oxide capacitance (Cox) in series with the depletion capacitance due to depletion region under gate oxide (CD).00.10.20.30.40.50.60.70.80.91-5 -4 -3 -2 -1 0 1 2 3 4 5VG-VFB (Volts)CG/Cox (Unitless)wn1min1wnoxDDCCCCDVGCoxsFS 2Fig. 1 : MOS normalized DC capacitance vs. voltage curve. From thiscurve the slope factor n can be estimated for a transistor. Nb=1016cm-3,Tox=150Ǻ, and the temperature is 300K. The flat band voltage (VFB) is0V.Figure 1 demonstrates how the slope factor in weak inversion (nW) can be extracted from MOS CV plot according to: nw=Cox+CDCox. (9) From Figure 1 it can be observed that the minimum valuefor gate capacitance (Cox) occurs when the surface potential is twice the substrate Fermi level (ΦF). Using this in equation (5) results in equation (9). Slope factor (n) can nowbe related to simple process parameters; doping levels and oxide thickness:n=nw min≃1+Γb2√2 ΦF(10)where the Fermi level (ΦF) is given by:ΦF=UTlnNbni (11)The ability to relate the slope factor of a transistor (n) to the slope factor of an MOS capacitor (nw) gives insight into transistor process design for high gain which can now be estimated from 1-D TCAD CV simulations or extracted fromMOS CV experiment on wafers. Extracting slope factor of an MOS capacitor (nw) from MOS CV experiments does not require wafer processing to include photolithography steps. An estimate of voltage gain (Av) can be obtained from wafers that have only gone through substrate implant, well drive, gate oxide growth, VT adjust and anneal processing steps before a mercury prove can be used to extract CV data to obtain (nw) .III. VERIFICATION METHODOLOGY OF ANALYTICALEQUATIONSA 4-Mask NMOS TCAD run deck with all transistor thermalprocess steps was simulated on Sentaurus Workbench (SWB) [2] to verify the time and temperatures for the well drive and the gate oxide. All other parameters were fixed, i.e. time and temperatures of screen oxide and field oxide. Table 1 shows design parameters used in this process.Time (minutes) Temp (Co)Screen Oxide 45 1100Well Drive 120 900Field Oxide 60 1100S/D diffusion 60 1100Gate Oxide 48 1000Table 2 : Thermal process steps for 4-Mask NMOS process.A TCAD 1-D simulation was conducted with the parameters from Table 1 along with a dose of 1.5×1015cm-2 and implantation energy of 100eV. Fixed oxide charge was assumed to be Qss = 5×1011q×cm-2. Table 2 summarizes the results extracted by the SWB simulation.Oxide Thickness (um)