Architectural Support for Operating SystemsAnnouncementsReview: History of OSReview: Migration of OS Concepts and FeaturesReview: Implementation Issues (How is the OS implemented?)Goals for Today and Next LectureComputer System ArchitectureI/O operationsAccessing I/O DevicesPolling I/OPolling I/O handshaking:Slide 12InterruptsEven interrupts are sometimes to slow:Direct Memory Access (DMA)Example I/OInterrupt TimelineModern interrupt handlingTraps and ExceptionsSlide 20Why Protection?Preventing Runaway ProgramsProtecting MemoryVirtual Memory / SegmentationProtected InstructionsDual-Mode OperationCrossing Protection BoundariesSystem CallsWhy APIs?Reducing System Call OverheadReal System Have HolesFixed Pie, Infinite DemandsFixed Pie, Infinite DemandArchitectural Support for Operating SystemsAnnouncements•Most office hours are finalized•Assignments (if any) up every Wednesday–Due one week later–Main TA to contact about assignments: Joy Zhang•Also contact, Barry Burton, Ashley Moore, Connie Wong, Tyler Steele•CS 415 sections started yesterday–Ari Rabkin is instructor•TA’s are Rohit Doshi, Ben Kraft, Jordan Crittenden, Syzmon Rozga–intro to the course and goals for the term–Overview of project and details on the first part of the project–C for Java programmers•syntax and similarities•common pitfalls•C software engineering•Optional architecture review session–215 Upson Hall, Thursday, 8-10pmReview: History of OS•Why Study?–To understand how user needs and hardware constraints influenced (and will influence) operating systems•Several Distinct Phases:–Hardware Expensive, Humans Cheap •Eniac, … Multics–Hardware Cheaper, Humans Expensive •PCs, Workstations, Rise of GUIs–Hardware Really Cheap, Humans Really Expensive •Ubiquitous devices, Widespread networking•Rapid Change in Hardware Leads to changing OS–Batch Multiprogramming Timeshare Graphical UI Ubiquitous Devices Cyberspace/Metaverse/??–Gradual Migration of Features into Smaller Machines•Situation today is much like the late 60s–Small OS: 100K lines/Large: 10M lines (5M browser!)–100-1000 people-yearsReview: Migration of OS Concepts and FeaturesReview: Implementation Issues(How is the OS implemented?)•Policy vs. Mechanism–Policy: What do you want to do?–Mechanism: How are you going to do it?–Should be separated, since policies changeGoals for Today and Next Lecture•I/O subsystem and device drivers•Interrupts and traps •Protection, system calls and operating mode•OS structure•What happens when you boot a computer?Computer System ArchitectureSynchronizes memory accessI/O operations•I/O devices and the CPU can execute concurrently.•I/O is moving data between device & controller’s buffer–CPU moves data between controller’s buffer & main memory•Each device controller is in charge of certain device type.–May be more than one device per controller•SCSI can manage up to 7 devices–Each device controller has local buffer, special registers•A device driver for every device controller–Knows details of the controller–Presents a uniform interface to the rest of OSAccessing I/O Devices•Memory Mapped I/O–I/O devices appear as regular memory to CPU–Regular loads/stores used for accessing device–This is more commonly used•Programmed I/O–Also called “channel” I/O–CPU has separate bus for I/O devices–Special instructions are required•Which is better?Polling I/O•Each device controller typically has:–Data-in register (for host to receive input from device)–Data-out (for host to send output to device)–Status register (read by host to determine device state)–Control register (written by host to invoke command)Polling I/O handshaking:•To write data to a device:1. Host repeatedly reads busy bit in status register until clear2. Host sets write bit in command register and writes output in data-out register3. Host sets command-ready bit in control register4. Controller notices command-ready bit, sets busy bit in status register5. Controller reads command register, notices write bit: reads data-out register and performs I/O (magic)6. Controller clears command-ready bit, clears the error bit (to indicate success) and clears the busy bit (to indicate it’s finished)Polling I/O•What’s the problem? –CPU could spend most its time polling devices, while other jobs go undone.•But devices can’t be left to their own devices for too long–Limited buffer at device - could overflow if doesn’t get CPU service.•Modern operating systems use Interrupts to solve this dilemma.CPUMemoryDeviceDataAddrR/WClockInterruptInterrupt PriorityInterrupts•CPU hardware has a interrupt-request line (a wire) it checks after processing each instruction. •On receiving signal save processing state–Save current context–Jump to interrupt handler routine at fixed address in memory–Interrupt handler:•Determine cause of interrupt.•Do required processing.•Restore state.•Execute return from interrupt instruction.•Device controller raises interrupt, CPU catches it, interrupt handler dispatches and clears it.•Most operating systems are interrupt-driven–Hardware: sends trigger on bus–Software: uses a system callEven interrupts are sometimes to slow:•Device driver loads controller registers appropriately•Controller examines registers, executes I/O•Controller signals I/O completion to device driver–Using interrupts•High overhead for moving bulk data (i.e. disk I/O):–One interrupt per byte..Direct Memory Access (DMA)•Transfer data directly between device and memory–No CPU intervention•Device controller transfers blocks of data •Interrupts when block transfer completed–As compared to when byte is completed•Very useful for high-speed I/O devicesExample I/OcacheCPU (*N)Thread ofexecutionMemoryInstructions and DataInstruction execution cycleData movementKeyboard Device Driverand Keyboard ControllerI/O RequestPerform I/ORead DataInterruptDataDisk Device Driverand Disk ControllerDMAInterrupt TimelineModern interrupt handling•Modern OS needs more sophisticated mechanism:–Ability to defer interrupt–Efficient way to dispatch interrupt handler–Multilevel interrupts to distinguish between high and low priority•Higher priority interrupts can pre-empt processing of lower priority ones –Use a specialized Interrupt Controller•CPUs typically have two interrupt request lines: –Maskable
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