3D IC technologyWhat is a 3D IC?Motivation3D Fabrication TechnologiesPerformance CharacteristicsTimingEnergy performanceEnergy performance graphsDesign tools for 3D-IC design3D Standard Cell tool Design3D Standard Cell PlacementTotal wire length vs. ViasTotal wire length vs. Vias (Cont)Intro to Global RoutingIllustration of routing areasHierarchical Global Routing2D Global RoutingIllustration of BisectionExtending to 3D3D Routing Results3D-MAGICConcerns in 3D circuitThermal Issues in 3D CircuitsHeat Flow in 2DHeat Flow in 3DHeat DissipationHeat Dissipation in Wafer Bonding versus Epitaxial GrowthHeat Dissipation in Wafer Bonding versus Epitaxial GrowthHigh epitaxial temperatureEMI in 3D ICsEMIReliability Issues?Implications on Circuit Design and ArchitectureBuffer InsertionLayout of Critical Paths and Microprocessor DesignMixed Signal ICs and Physical DesignConclusion3D IC technologyPouya DormianiChristopher LucasWhat is a 3D IC?“Stacked” 2D (Conventional) ICsCould be Heterogeneous…MotivationInterconnect structures increasingly consume more of the power and delay budgets in modern designPlausible solution: increase the number of “nearest neighbors” seen by each transistor by using 3D IC designSmaller wire cross-sections, smaller wire pitch and longer lines to traverse larger chips increase RC delay.RC delay is increasingly becoming the dominant factorAt 250 nm Cu was introduced alleviate the adverse effect of increasing interconnect delay. 130 nm technology node, substantial interconnect delays will result.3D Fabrication TechnologiesMany options available for realization of 3D circuitsChoice of Fabrication depends on requirements of Circuit SystemBeam RecrystallizationProcessed Wafer BondingSilicon Epitaxial GrowthSolid Phase CrystallizationDeposit polysillicon and fabricate TFTs-not practial for 3D circuits due to high temp of melting polysillicon-Suffers from Low carrier mobility-However high perfomance TFT’shave been fabricated using low temp processing which can be used to implement 3D circuitsBond two fully processed wafers together.-Similar Electrical Properties on all devices-Independent of temp. since all chips are fabricated then bonded-Good for applications where chips do independent processing-However Lack of Precision(alignemnt) restricts interchip communication to global metal lines.Epitaxially grow a single cystal Si -High temperatures cause siginificant cause significant degradation in quality of devices on lower layers-Process not yet manufacturableLow Temp alternative to SE.-Offers Flexibilty of creating multiple layers-Compatible with current processing environments-Useful for Stacked SRAM and EEPROM cellsPerformance CharacteristicsTimingEnergyWith shorter interconnects in 3D ICs, both switching energy and cycle time are expected to be reducedTimingIn current technologies, timing is interconnect driven.Reducing interconnect length in designs can dramatically reduce RC delays and increase chip performanceThe graph below shows the results of a reduction in wire length due to 3D routingDiscussed more in detail later in the slidesEnergy performanceWire length reduction has an impact on the cycle time and the energy dissipationEnergy dissipation decreases with the number of layers used in the designFollowing graphs are based on the 3D tool described later in the presentationEnergy performance graphsDesign tools for 3D-IC designDemand for EDA toolsAs the technology matures, designers will want to exploit this design areaCurrent tool-chainsMostly academicWe will discuss a tool from MIT3D Standard Cell tool Design3D Cell PlacementPlacement by min-cut partitioning3D Global RoutingInter-wafer viasCircuit layout managementMAGIC3D Standard Cell PlacementNatural to think of a 3D integrated circuit as being partitioned into device layers or planesMin cut part-itioning along the 3rd dimension is same as minimizing viasTotal wire length vs. ViasCan trade off increased total wire length for fewer inter-plane vias by varying the point at which the design is partitioned into planesPlane assignment performed prior to detailed placementYields smaller number of vias, but greater overall wire lengthTotal wire length vs. Vias (Cont)Plane assignment not made until detailed placement stageYields smaller total wire length but greater number of viasIntro to Global RoutingOverviewGlobal Routing involves generating a “loose” route for each net.Assigns a list of routing regions to a net without actually specifying the geometrical layout of the wires.Followed by detailed routingFinds the actual geometrical shape of the net within the assigned routing regions.Usually either sequential or hierarchical algorithmsIllustration of routing areasxzyxzyDetailed routing of net when routing areas are knownHierarchical Global RoutingTool uses a hierarchical global routing algorithmBased on Integer programming and Steiner treesInteger programming approach still too slow for size of problem and complexity (NP-hard)Hierarchical routing methods break down the integer program into pieces small enough to be solved exactly2D Global RoutingA 2D Hierarchical global router works by recursively bisecting the routing substrate.Wires within a Region are fully contained or terminate at a pin on the region boundry.At each partitioning step the pins on the side of the routing region is allocated to one of the two subregions.Wires Connect cells on both sides of the partition line.These are cut by the partition and for each a pin is inserted into the side of the partitionOnce complete, the results can be fed to a detailed router or switch box router (A switchbox is a rectangular area bounded on all sides by blocks)Illustration of BisectionExtending to 3DRouting in 3D consists of routing a set of aligned congruent routing regions on adjacent wafers.Wires can enter from any of the sides of the routing region in addition to its top and bottom3D router must consider routing on each of the layers in addition to the placement of the inter-waver viasBasis idea is: You connect a inter-waver via to the port you are trying to connect to, and route the wire to that via on the 2D plane.All we need now is enough area in the 2D routing space to route to the appropriate via3D Routing ResultsPercentage Of 2D Total wire LengthMinimizing for Wire