1. INTRODUCTION2. LEAKAGE CURRENTS IN SCALED DEVICES2.1 Subthreshold Leakage2.2 Gate Direct Tunneling Current2.3 Junction Tunneling Current2.4 Inter-Dependence of Different Leakage Components3. CIRCUIT TECHNIQUES TO REDUCE LEAKAGE3.1 Design Time Techniques3.1.1 Dual Threshold CMOS3.2 Run Time Techniques3.2.1 Standby Leakage Reduction Techniques3.2.1.1 Natural Transistor Stacks3.2.1.2 Sleep Transistor (Forced Stacking)3.2.1.3 Forward/Reverse Body Biasing3.2.2 Active Leakage Reduction Techniques3.2.2.1 Dynamic Vth Scaling (DVTS)4. PROCESS VARIATION AND LEAKAGE5. CIRCUIT TECHNIQUES FOR COMPENSATING PROCESS VARIATION5.1 Adaptive Body Biasing for Process Compensation5.2 Process Variation Compensation in Dynamic Circuits6. CONCLUSIONS7. ACKNOWLEDGEMENT8. REFERENCESLeakage Mechanisms and Leakage Control for Nano-ScaleCMOS CircuitsAmit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, and Kaushik RoySchool of Electrical and Computer Engineering, Purdue UniversityWest Lafayette, IN 47906, USA001-765-494-2361<amita, hyungil, sm, [email protected]>ABSTRACTThe high leakage current in nano-meter regimes is becoming asignificant contributor to power dissipation of CMOS circuits asthreshold voltage, channel length, and gate oxide thickness arereduced. Consequently, the identification of different leakagecomponents is very important for estimation and reduction ofleakage. Moreover, the increasing statistical variation in theprocess parameters has emerged as a serious problem in thenano-scaled circuit design and can cause significant variation inthe transistor leakage current across and within different dies.Designing with the worst case leakage may cause excessiveguard-banding, resulting in a lower performance. This paperexplores various intrinsic leakage mechanisms including weakinversion, gate-oxide tunneling and junction leakage etc. Variouscircuit level techniques to reduce leakage energy and their designtrade-off is discussed. We also explore process variationcompensating techniques to reduce delay and leakage spread,while meeting power constraint and yield.Categories and Subject DescriptorsB.3.7.1 [Integrated Circuits]: Types and Design Styles -Microprocessors and microcomputers, VLSI.General Terms: Design, Performance, Experimentation.Keywords: Leakage current, Circuit design, Processvariation.1. INTRODUCTIONCMOS devices have been scaled down aggressively in eachtechnology generations to achieve higher integration density andperformance. However, the leakage current has increaseddrastically with technology scaling and has become a majorcontributor to the total IC power. Moreover, the increasingstatistical variation in the process parameters has emerged as aserious problem in the nano-scaled circuit design and can causesignificant increase in the transistor leakage current. Designingwith the worst case leakage may cause excessive guard-banding,resulting in a lower performance. Hence, accurate estimation ofthe total leakage current considering the effect of randomvariations in the process parameters is extremely important fordesigning CMOS circuits in the nano-meter regime.Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on the first page. To copy otherwise, orrepublish, to post on servers or to redistribute to lists, requires prior specificpermission and/or a fee.Conference’04, Month 1–2, 2004, City, State, Country.Copyright 2004 ACM 1-58113-000-0/00/0004…$5.00.Different leakage mechanisms contribute to the total leakage in adevice. Among them, the three major ones can be identified as:Subthreshold leakage, Gate leakage and Reverse biased drain-substrate and source-substrate junction Band-To-Band-Tunnelingleakage [1-2]. In scaled devices each of these leakagecomponents increases drastically resulting in a dramatic increasein the total leakage current. Moreover, each component dependsdifferently on the transistor geometry (gate length (Lg), Source-Drain extension length (LSDE), oxide thickness (Tox), junctiondepth (Yj), width (W)), the doping profile (channel doping (Ndep)and “halo” doping (Npocket) concentration), the flat-band voltage(Vfb), and the supply voltage (Vcc) [2]. Hence, statistical variationin each of these parameters results in a large variation in each ofthe leakage components, thereby, causing significant changes inthe nominal leakage and delay. In the nano-meter regime, asignificant portion of the total power consumption in highperformance digital circuits is due to leakage currents. Becausehigh performance systems are constrained to a predefined powerbudget, the leakage power reduces the available power,impacting performance. It also contributes to the powerconsumption during standby operation, reducing battery life.Hence, techniques are necessary to reduce leakage power whilemaintaining the high performance. This power and performance trade off is becoming worse withprocess variation. Process parameter variation, which isincreasing as technology scales, impacts the frequency andleakage distribution of fabricated chips [3]. It can be observedthat there is a correlation between the leakage power and thefrequency of operation. Because of die-to-die and within dievariations, many dies may not achieve the desired frequencytarget, while others may fail the maximum leakage powerspecification. Leakage spread poses stringent design trade-off inleakage sensitive circuits, e.g wide-OR domino gate, to achievehigh performance while maintaining sufficient yield [4]. Processcompensating techniques that reduce the delay and leakagespread, while meeting power constraint and high yield areindispensable in future design. Reverse Biased Junction BTBT Gate Source n+ n+ Bulk Drain Subthreshold Leakage Gate Leakage Figure 1. Major leakage mechanisms in a CMOS device.This paper is organized as follows.