EE 201A/EE298 Modeling and Optimization for VLSI LayoutOutlineInstructor InfoAbout this CourseCourse PrerequisitesEE205A and EE205BVLSI Design CycleVLSI Design Cycle (cont.)Simplified Physical Design CycleCourse Outline and ScheduleRelated VLSI CAD ConferencesRelated VLSI CAD JournalsMoney Talk for VLSI CADReferences for this CourseGrading PolicyCourse Presentation (15%)Term Project (50%)Who should take this courseComplexities of Physical DesignMoore’s Law and NTRSProductivity GapDesign Challenges in Nanometer TechnologiesDesign StylesFull Custom Design StyleStandard Cell Design StyleGate Array Design Style (or Structured ASIC)Field-Programmable Gate-Arrays (FPGAs)FPGA Design StyleComparisons of Design StylesSlide 30Packaging StylesPrinted Circuit Board ModelMCM ModelWafer Scale IntegrationComparisons of Packaging StylesIncreasingly on the Same Chip or in the Same Package (SoC and SiP)History of VLSI Layout ToolsSummaryHomework (due April 14th)EE 201A/EE298Modeling and Optimization for VLSI Layout Instructor: Lei HeEmail: [email protected]Course logisticsCourse logisticsOverviewOverviewWhat are covered in the courseWhat are covered in the courseWhat are interesting trends for physical designWhat are interesting trends for physical designInstructor InfoEmail: [email protected]: [email protected]Phone: 310-206-2037Phone: 310-206-2037Office: Engineering IV 68-117Office: Engineering IV 68-117Office hours: Tu/Th 2-3pm or by Office hours: Tu/Th 2-3pm or by appointmentappointmentThe best way to reach me: The best way to reach me: Email with EE201 in subject lineEmail with EE201 in subject lineAbout this CourseOne of selective course for EE’s ECS Major Field StudentsOne of selective course for EE’s ECS Major Field StudentsQuestion in M.S. comprehensive exam / PhD prelimsQuestion in M.S. comprehensive exam / PhD prelimsOffered every other springOffered every other springWill be under another course number (EE205B)Will be under another course number (EE205B)Related coursesRelated coursesMani’s EE202A Embedded Computing Systems (Fall)Mani’s EE202A Embedded Computing Systems (Fall)Ingrid’s EE201A on Advanced VLSI (Spring)Ingrid’s EE201A on Advanced VLSI (Spring)Bill M-S’s EE204A on Compilers (Winter)Bill M-S’s EE204A on Compilers (Winter)My EE205A Fundamental to CAD (Winter)My EE205A Fundamental to CAD (Winter)Mani’s EE206A Wireless Systems (Spring)Mani’s EE206A Wireless Systems (Spring)My EE205B (every other Spring)My EE205B (every other Spring)Course PrerequisitesOfficial prerequisiteOfficial prerequisiteEE116BEE116B VLSI System DesignVLSI System DesignBut mainly self-containedBut mainly self-containedKnowledge to help you appreciate moreKnowledge to help you appreciate moreCS180CS180Introduction to algorithmsIntroduction to algorithmsEE205A and EE205BEE205A Fundamental to CAD of embedded systemsEE205A Fundamental to CAD of embedded systemsSystem level performance/power/thermal modeling and System level performance/power/thermal modeling and optimizationoptimizationSynthesis – scheduling and allocation, logic optimization Synthesis – scheduling and allocation, logic optimization and technology mappingand technology mappingFPGA circuits and architectures and placement and FPGA circuits and architectures and placement and routing for FPGArouting for FPGAEE205B Modeling and Optimization for VLSI layoutEE205B Modeling and Optimization for VLSI layoutAdvanced algorithms for physical designAdvanced algorithms for physical designFundamentals of combinatorial algorithmFundamentals of combinatorial algorithmDetailed performance, signal integrity, power and thermal Detailed performance, signal integrity, power and thermal modelsmodelsIncorporating physical design into system designIncorporating physical design into system designSystem SpecificationFunctional DesignLogic DesignCircuit DesignX=(AB*CD)+(A+D)+(A(B+C))Y=(A(B+C))+AC+D+A(BC+D))VLSI Design CyclePhysical DesignFabricationPackagingVLSI Design Cycle (cont.)PartitionFloorplanningPlacementSimplified Physical Design CycleRoutingExtraction and VerificationFront-endFront-endphysical designphysical designBack-endBack-endphysical designphysical designCourse Outline and ScheduleFront-end physical design (4.5 weeks)Front-end physical design (4.5 weeks)Partitioning, floorplanning and placementPartitioning, floorplanning and placementPower and thermal modelingPower and thermal modelingAlgorithms: divided and conquer, simulated annealing, genetic algorithmAlgorithms: divided and conquer, simulated annealing, genetic algorithmProject proposal due by end of fifth weekProject proposal due by end of fifth weekBack-end physical design (4.5 weeks)Back-end physical design (4.5 weeks)Interconnect extraction and modeling Interconnect extraction and modeling Interconnect synthesisInterconnect synthesisNoise modeling and avoidanceNoise modeling and avoidanceClock and power supply design **Clock and power supply design **Algorithms: dynamic programming, linear programmingAlgorithms: dynamic programming, linear programmingProject report due the last day of the quarterProject report due the last day of the quarter ACM IEEE Design Automation Conference (DAC) http://www.dac.com (San Diego, Young student program) International Conference on Computer Aided Design(ICCAD) Design, Automation and Test in Europe (DATE) Asia and South Pacific Design Automation Conference (ASP-DAC) International symposium on physical design (ISPD) International symposium on low power electronics and design International symposium on field programmable gate array IEEE International Symposium on Circuits and Systems (ISCAS)Related VLSI CAD Conferences IEEE Transactions on CAD of Circuits and systems (TCAD) ACM Trans. on Design Automation of Electronic Systems (TODAES) IEEE Transactions on Circuits and Systems (TCAS) IEEE Trans. on VLSI Systems (TVLSI) IEEE Trans. on Computer Integration Algorithmica SIAM journal of Discrete and Applied MathematicsRelated VLSI CAD Journals Synposys, Cadence, Magma, Mentor Graphics, … Over hundreds companies have booths at DAC Two of them are among the ten biggest software companies in the worldBut they are smaller than the biggest spin-off of EDA EDA is regarded as A-graded bonds for Venture