UCLA ELENGR 201A - Fabrication Technologies for Three-Dimensional Integrated Circuits

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Fabrication Technologies for Three-Dimensional Integrated Circuits Rafael Reif Dept. of Electrical Engineering and Computer Science, MIT Cambridge, MA [email protected] Andy Fan Dept. of Electrical Engineering and Computer Science, MIT Cambridge, MA [email protected] Kuan-Neng Chen Dept. of Materials Science and Engineering, MIT Cambridge, MA [email protected] Shamik Das Dept. of Electrical Engineering and Computer Science, MIT Cambridge, MA [email protected] Abstract The MIT approach to 3-D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: a) Structural integrity of the Cu-Cu bond, b) Cu-Cu contact electrical characteristics, and c) Process flow efficiency and repeatability. In addition, CAD tools are needed to aid in design and layout of 3DICs. This paper will discuss recent results in all these areas. 1. Introduction Three-dimensional integrated circuits (3DICs) have attracted attention in industry and academia as it may provide an enabling technology that relaxes today's interconnect-bottleneck. As device densities continue to increase with advances in lithography and device design, device-to-device interconnects will continue to be a major design issue. The ITRS 99 roadmap projects that the number of metal layers at the 50-nm generation will be 9-10. With current manufacturing technologies, it will be a major challenge for future designs to be able to manage such complexity while maintaining the performance improvements that the market demands. Multi-layer device structures such as 3D-ICs, are seen as a possible solution for this challenge. It can be shown that 3-D architectures can reduce the overall global and semi-global wire-length, while increasing the number of local wires [1]. Moreover, the decrease in the number of long interconnects could directly translate to an increase in device density, provided that the devices are efficiently packed, placed, and wired. In addition to these potential benefits, the 3-D architecture lends itself to the realization of a "system-on-a-chip." Monolithic mixed-technology options, such as 3-D imagers, have already shown promise [2,3]. Other opportunities, such as OEIC-on-Si technology, memory-on-logic, and various microelectromechanical (MEMS) hybrids are also possible. There exist a plethora of 3-D integration techniques in literature, but the two most appealing and competitive schemes to date are those involving either low-temperature silicon epitaxy or wafer bonding. The central theme between these two methods is vertical integration - namely, the addition of CMOS devices on top of each other. Their inherent differences, however, are of course the stacking technique itself, as well as each scheme's potential for high vertical connectivity and "system-on-a-chip" integration. For instance, in the epitaxy scheme, multiple device layers can be realized by repeating the "Si epitaxy followed by a CMOS flow" cycle" [4], where successive device layers are fabricated in serial mode. The enabling technology is a well-characterized low-temperature Si epitaxy, which is crucial for thermal budget minimization of the process flow. Layer-to-layer connections can made from either inter-layer vias (as in [4]) or from direct source-drain / source-drain contacts using sandwiched polysilicon lines. In theory, the combination of Si epitaxy with local poly-Si interconnects would probably create a true 3-D system, where it will contain the highest vertical connectivity of all current 3-D schemes. But 3-D integration with serial Si epitaxy comes with a price: It will be very difficult to implement circuit integration with mixed-technologies (i.e. III-V optics with CMOS). On the other hand, in the wafer bonding approach, integration of mixed technologies is of second nature. In most wafer bonding schemes [2,3,5,6], multiple device wafers in the stack are held together with adhesives (i.e. polymers, metal-to-metal thermocompression, low-melting point eutectic solders, etc.), and inter-layer vias provide layer-to-layer communication. Although the process flows do vary significantly, most wafer bonding schemes share four common considerations: a) The bonding medium ("glue") of choice, b) If needed, a method for Si substrate thinning, c) The wafer-to-wafer alignment accuracy, and d) The inter-layer electrical interconnection method. To be specific, the remainder of this paper will focus on these Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEEconsiderations that apply to 3-D integration with Cu-Cu wafer bonding. 2. Process Flow In our 3-D integration scheme, multiple device wafers are sequentially bonded to each other using low-temperature Cu-Cu thermocompression. Figure 1 depicts our definition of a 3-D circuit, in which two device layers are both bonded and electrically interconnected using Cu-Cu pads (the bonding interface). Figure 1. A typical 3-D circuit The ideal case for such architecture is to have the smallest possible lateral dimensions for the Cu pads and inter-wafer vias to ensure high via density. In reality, wafer-wafer alignment tolerances during bonding and the maximum aspect ratio of the vias one can create will ultimately be the size-limiting determinants of these vias / Cu pads (see Section 2.3). As shown in Figure 1, when the top device layer is a thin SOI, the aspect ratio of the inter-wafer vias can be relaxed to around 3:1 or even 2:1 for ease in fabrication, while still maintaining a relatively high vertical density across the wafer. To recapitulate, the goal of our process flow is to create a 3-D stack by successive bonding of SOI device layers on top of each other. Figure 2 is a flowchart of such a process, in which the 3-D stack begins with bonding of two device wafers, and subsequent device layers can be added to the stack in a short turn-around process loop. As seen in this chart, the majority of the processing steps revolve around the preparation of the first SOI substrate prior to bonding (mainly for substrate thinning), which is the focus of the next three subsections. Figure 2. Process flowchart 2.1. Handle Wafer Attachment Our 3-D scheme begins with a typical SOI substrate (100 nm SOI / 400 nm BOX)


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UCLA ELENGR 201A - Fabrication Technologies for Three-Dimensional Integrated Circuits

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