UCLA ELENGR 201A - Fabrication Technologies for Three-Dimensional Integrated Circuits (5 pages)

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Fabrication Technologies for Three-Dimensional Integrated Circuits



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Fabrication Technologies for Three-Dimensional Integrated Circuits

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Pages:
5
School:
University of California, Los Angeles
Course:
Elengr 201a - VLSI Design Automation
VLSI Design Automation Documents

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Fabrication Technologies for Three Dimensional Integrated Circuits Rafael Reif Dept of Electrical Engineering and Computer Science MIT Cambridge MA reif mit edu Andy Fan Dept of Electrical Engineering and Computer Science MIT Cambridge MA fana mit edu Abstract The MIT approach to 3 D VLSI integration is based on low temperature Cu Cu wafer bonding Device wafers are bonded in a face to back manner with short vertical vias and Cu Cu pads as the inter wafer throughway In our scheme there are several reliability criteria which include a Structural integrity of the Cu Cu bond b CuCu contact electrical characteristics and c Process flow efficiency and repeatability In addition CAD tools are needed to aid in design and layout of 3DICs This paper will discuss recent results in all these areas 1 Introduction Three dimensional integrated circuits 3DICs have attracted attention in industry and academia as it may provide an enabling technology that relaxes today s interconnect bottleneck As device densities continue to increase with advances in lithography and device design device to device interconnects will continue to be a major design issue The ITRS 99 roadmap projects that the number of metal layers at the 50 nm generation will be 910 With current manufacturing technologies it will be a major challenge for future designs to be able to manage such complexity while maintaining the performance improvements that the market demands Multi layer device structures such as 3D ICs are seen as a possible solution for this challenge It can be shown that 3 D architectures can reduce the overall global and semi global wire length while increasing the number of local wires 1 Moreover the decrease in the number of long interconnects could directly translate to an increase in device density provided that the devices are efficiently packed placed and wired In addition to these potential benefits the 3 D architecture lends itself to the realization of a system on a chip Monolithic mixed



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