UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180A DIGITAL SYSTEMS I Summer 2005 LAB 6: SEQUENTIAL NETWORK DESIGN In this lab, you will gain experience in the design and testing of sequential circuits. It is essential that you prepare thoroughly for this lab. Hardware Required: 1 pc. PALCE22V10 Programmable Logic Device Preparation (Pre-lab) Do the complete paper design of the state machine specified below implemented using J-K flip-flops. Derive a state diagram and a state transition table. Encode the states, draw appropriate K-maps and derive the J-K flip-flop input equations. Determine the output equation based on the state bits. I. Design of a State Machine There are two variations to this lab exercise. Students with an odd student id number will do the sequence detector based on problem 16.7 from Charles Roth’s textbook Fundamentals of Logic Design, Fifth Edition. Students with an even student id number will do the sequence detector based on problem 16.9 of the same text. For either sequence detector, the sequential network will monitor a serial input X and produce an output Z. A block diagram of the sequence detector circuit is shown in Figure 1. Sequential Network to be DesignedX Z clock(debounced switch)resetFigure 1: Block Diagram Problem 16.7 Design a clocked Mealy sequential network which investigates an input sequence X and which will produce an output of Z=1 if the total number of 1’s received is even (consider zero 1’s to be an even number of 1’s) and the sequence 00 has occurred at least once. Note: The total number of 1’s received includes those received before and after 00.Example: X = 1 0 1 0 1 0 0 1 1 0 1 Z = 0 0 0 0 0 0 0 1 0 0 1 Notice that the circuit does not reset to the start state when an output of Z=1 occurs. However, your circuit should have a start state and should be provided with a method of manually resetting the flip-flops to the start state. A minimum solution requires 6 states. Problem 16.9 Design a Mealy sequential network which investigates an input sequence X and produces an output Z which is determined by two rules. The initial output from the network is Z=0. Thereafter, the output Z will equal the preceding value of X (rule 1) until the input sequence 001 occurs. Starting with the next input after 001, the output Z will equal the complement of the present value of X (rule 2) until the sequence 100 occurs. Starting with the next input after 100, the network output is again determined by rule 1, etc. Note that overlapping 001 and 100 sequences may occur. Example: Rule: 1 1 1 1 2 2 2 2 2 1 1 2 X = 1 0 0 1 1 0 1 0 0 0 1 1 Z = 0 1 0 0 0 1 0 1 1 0 0 0 Your circuit should be provided with a method for manually resetting the flip-flops to the start state. A minimum solution requires 6 states. Part I: Using Gates and J-K Flip-flops Enter and simulate your circuit in Quartus II using a minimal number of J-K flip-flops, 2-, 3-, and 4- input NAND gates. Demonstrate your simulation to your TA and print out the schematic and waveform files. Part II: Using a Programmable Logic Device Your entire sequential network can be implemented in a PALCE22V10. In a previous lab, you used a PALCE22V10 to implement a combinational network. Here, you will use the registered outputs for implementing your state machine. An example file that illustrates a simple state machine design is shown in Figure 2. Notice that your clock input must be on pin 1. Your state bits must be defined as registered outputs. As mentioned in Lab 4, if you are programming a /4 type device, you should specify the device as PALCE22V10. Follow the example shown in Figure 2 for implementing a global reset input. The PALCE22V10 has internal D-type flip-flops. Therefore, you will need to use the state transition table and next-state K-maps to derive the D input equations. Using the PALASM software, enter your design equations for the sequence detector. Program your PALCE22V10 and verify its operation in circuit. Demonstrate your circuit to the TA for verification. Lab ReportEach individual will be required to submit a lab report. Use the format specified in the "Lab Report Information" document available on the class web page. Be sure to include the following items in your lab report:  Lab cover sheet with TA verification for circuit simulation and performance  Graded pre-lab  Minimized state diagram for your circuit  The state encoding you selected, state transition table, K-maps and the final equations  A final schematic of your circuit  Your PALASM file Lab Grading Total=100 (Pre-lab=20 / Lab Verification=50 / Lab Report=30) (a) Before coming to lab, make sure you have the complete state diagram (with the number of states minimized as much as you can), the state transition table, the K-maps and the final circuit. Preferably, simulate your circuit in Quartus II. (b) Demonstrate the PLD version of the sequence detector. (c) Report will be graded as follows: Minimized state diagram 5 State transition table 5 K-Maps (for JK and PAL designs) 5 Final circuit schematics (for JK and PAL designs) 5 PALASM file 5 Neatness, style, etc. 5;----------------------------------- PALASM EXAMPLE FILE -- PALASM Design Description ;---------------------------------- Declaration Segment ------------ TITLE EXAMPLE SEQUENCE DETECTOR PATTERN REVISION AUTHOR LH COMPANY UCD DATE 12/19/94 CHIP MOORE PALCE22V10 ; Design specifications: Moore sequential network that investigates ; an input sequence X and produces an output of Z=1 for any input ; sequence ending in 0110 or 101. ;---------------------------------- PIN Declarations --------------- PIN 1 CLOCK ; INPUT PIN 2 RESET ; INPUT PIN 3 X ; INPUT PIN 12 GND ; INPUT PIN 20 Q0 REGISTERED ; OUTPUT PIN 21 Q1 REGISTERED ; OUTPUT PIN 22 Q2 REGISTERED ; OUTPUT PIN 23 Z COMBINATORIAL ; OUTPUT PIN 24 VCC ; INPUT NODE 1 GLOBAL ; INPUT ;----------------------------------- Boolean Equation Segment ------ EQUATIONS GLOBAL.RSTF = RESET