UNIVERSITY OF CALIFORNIA, DAVISDepartment of Electrical and Computer EngineeringEEC180A DIGITAL SYSTEMS ILAB 8: SEQUENTIAL CIRCUIT DESIGNIn this lab, you will gain experience in the design and testing of sequential circuits. It is essentialthat you prepare thoroughly for this lab.Hardware Required:2 pcs. 74LS73A Dual negative-edge-triggered J-K Flip-Flopsas needed 74LS00 Quad 2-input NAND gateas needed 74LS10 Triple 3-input NAND gate1 pc. PALCE22V10 Programmable Logic DevicePreparation (Pre-lab)Do the complete paper design of the state machine specified below implemented using J-Kflip flops. Derive a state diagram and a state transition table. Encode the states, draw appropriateK-maps and derive the J-K flip-flop input equations. Determine the output equation based on thestate bits.State Machine SpecificationsDesign a Moore sequential network which monitors a serial input X and produces an output of Z=1when a specific sequence, described below, is detected. Otherwise, Z=0. A block diagram of thecircuit is shown in Figure 1.SequentialNetworkCLOCK(debounced switch)RESETXZFigure 1: Block diagramThe sequence detector that you will design should meet the following specifications:a) An output of Z=1 must be produced whenever the last string of four input bits startedwith a 1 and contained either two or four 1's total.b) After receiving a 1 to start the string, the sequence detector must analyze the next threebits of the string before it looks for the next string. This must occur regardless ofwhether an output of Z=1 is produced.An example input / output sequence is shown below, where the sequence proceeds from left toright. The start of a string of four inputs to be analyzed is shown by an up arrow beneath theinput. Note that the output will be delayed slightly from the input by propagation delays.INPUT: 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 ^ ^ ^ ^ ^OUTPUT: 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1Part I: Using Gates and JK Flip-flopsBuild your circuit using a minimal number of JK flip-flops, 2- and 3- input NAND gates. Don'tforget to build the debounce circuit for the switch input. Demonstrate the circuit to your TA.Part II: Using a Programmable Logic DeviceYour entire sequential network can be implemented in a PALCE22V10. In a previous lab, youused a PALCE22V10 to implement a combinational network. Here, you will use the registeredoutputs for implementing your state machine. An example file which illustrates a simple statemachine design is shown in Figure 2. Notice that your clock input must be on pin 1. Your statebits must be defined as registered outputs. As mentioned in lab 5, you should specify the deviceas PALCE22V10. Follow the example shown in Figure 2 for implementing a global reset input.The PALCE22V10 has internal D-type flip-flops. Therefore, you will need to use the statetransition table and next-state K-maps to derive the D input equations.Using the PALASM software, enter your design equations for the state machine. Program yourPALCE22V10 and verify its operation in circuit. Demonstrate your circuit to the TA forverification.Lab ReportEach student must submit a lab report. Your lab report should include the minimized statediagram, the state encoding you selected, the state transition table, the K-maps and the finalequations. Also include the final schematic of your circuit and your PALASM file.;----------------------------------- PALASM EXAMPLE FILE --PALASM Design Description;---------------------------------- Declaration Segment ------------TITLE EXAMPLE SEQUENCE DETECTORPATTERNREVISIONAUTHOR LHCOMPANY UCDDATE 12/19/94CHIP MOORE PALCE22V10; Design specifications: Moore sequential network which investigates; an input sequence X and produces an output of Z=1 for any input; sequence ending in 0110 or 101.;---------------------------------- PIN Declarations ---------------PIN 1 CLOCK ; INPUTPIN 2 RESET ; INPUTPIN 3 X ; INPUTPIN 12 GND ; INPUTPIN 20 Q0 REGISTERED ; OUTPUTPIN 21 Q1 REGISTERED ; OUTPUTPIN 22 Q2 REGISTERED ; OUTPUTPIN 23 Z COMBINATORIAL ; OUTPUTPIN 24 VCC ; INPUTNODE 1 GLOBAL ; INPUT;----------------------------------- Boolean Equation Segment ------EQUATIONSGLOBAL.RSTF = RESET ; When reset input is high, registered outputs resetQ0 = Q2*/X + Q2*Q1*/Q0 + /Q2*Q0*X + /Q1*/XQ1 = /Q1*X + Q2*Q0*X + /Q2*/Q0*X + Q2*/Q1*Q0Q2 = Q2*/Q0*X + Q1*Q0*X + /Q2*Q1*/X + Q2*/Q1*Q0*/XZ = Q2*Q1;----------------------------------- Simulation Segment ------------SIMULATIONtrace_on CLOCK X Z Q0 Q1 Q2 RESETsetf RESET Xclockf CLOCKsetf /RESETclockf CLOCKsetf /Xclockf CLOCKsetf Xclockf CLOCKcheck Zclockf CLOCKsetf /Xclockf CLOCKcheck Zsetf Xclockf CLOCKcheck Ztrace_off;-------------------------------------------------------------------Figure 2: Example PALASM input