# UT CS 310 - State Machines (11 pages)

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## State Machines

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## State Machines

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Pages:
11
School:
University of Texas at Austin
Course:
Cs 310 - Computer Organization and Programming
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State Machines University of Texas at Austin CS310 Computer Organization Spring 2009 Don Fussell Another look at D latch flip flop qold D qnew 0 0 1 1 0 1 0 1 0 1 0 1 This is an example of a state diagram more specifically a Moore machine qnew D University of Texas at Austin CS310 Computer Organization Spring 2009 Don Fussell 2 Synchronous state machines If a system can both process and store information then the values stored in the memory elements depend on both the inputs and the previous values in these elements This is called a sequential system Such a system is also called a finite state machine FSM If all changes to memory values happen at the same time as determined by a global system clock we have a synchronous FSM University of Texas at Austin CS310 Computer Organization Spring 2009 Don Fussell 3 FSM definition An FSM has the following components A set of states A set of inputs A set of outputs A state transition function of the states and inputs An output function of the states and maybe inputs Moore machine function of states only Mealy machine function of states and inputs This can be represented by a state diagram States are circles Arcs show the state transition function Arcs are labeled with input values Outputs are labels on states Moore or arcs Mealy University of Texas at Austin CS310 Computer Organization Spring 2009 Don Fussell 4 Another example 2 bit counter Counter starts at 0 green and increments each time the clock cycles until it gets to 3 and then overflows back to 0 Only input is the clock we don t show that Hold Lold Hnew Lnew 0 0 1 1 University of Texas at Austin 0 1 0 1 CS310 Computer Organization 0 1 1 0 1 0 1 0 Spring 2009 Don Fussell 5 2 bit counter Hold Lold Hnew Lnew 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 Lnew Hold Lold HoldLold Lold Hnew Hold Lold HoldLold University of Texas at Austin CS310 Computer Organization Spring 2009 Don Fussell 6 2 bit counter with reset R Hold Lold Hnew Lnew 0 0 0 0 1 Lnew R Hold Lold R HoldLold R Lold R Lold University of Texas at Austin 0 0 1 1 x 0 1 0 1 x 0 1 1 0 0 1 0 1 0 0 Hnew R Hold Lold R HoldLold R Hold Lold HoldLold CS310 Computer Organization Spring 2009 Don Fussell 7 2 bit counter with reset University of Texas at Austin CS310 Computer Organization Spring 2009 Don Fussell 8 Counter with 7 segment display Each segment in the display can be lit independently to allow all 10 decimal digits to be displayed also hex 2 bit counter will need to display digits 0 3 so will output a 1 for each segment to be lit for a given state University of Texas at Austin CS310 Computer Organization Spring 2009 Don Fussell 9 Counter with output functions R Ho Lo Hn Ln A B C D E F G 0 0 0 0 1 0 1 0 1 x 0 1 1 0 0 1 0 1 0 0 1 0 1 1 0 0 0 1 1 x 1 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 A D R Ho Lo R HoLo R HoLo R Ho Lo B R C R HoLo F R Ho Lo R Ho Lo University of Texas at Austin E R Lo G R Ho CS310 Computer Organization Spring 2009 Don Fussell 10 7 segment output logic University of Texas at Austin CS310 Computer Organization Spring 2009 Don Fussell 11

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