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Combinational LogicMulti-input gates - (x+(y*z))’Half AdderFull 1-bit adderCMOS adderMultiplexor2 input Multiplexor designMaking bigger muxesDecodersProgrammable Logic Array (PLA)University of Texas at Austin CS310 - Computer Organization Spring 2009 Don FussellCombinational LogicUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 2Multi-input gates - (x+(y*z))’yxOutVddzx y z out0 0 0 10 0 1 10 1 0 10 1 1 01 0 0 01 0 1 01 1 0 01 1 1 0Very easy with inverting gatesUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 3Half Adder1-bit addition (x + y) outputs: sum s and carry c s = xy’ + x’y (x XOR y or x  y) c = xyx y s c0 0 0 00 1 1 01 0 1 01 1 0 1xyscUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 4Full 1-bit adderNeed a carry in cix ycisco0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1 s = x’yci’+ xy’ci’ + x’y’ci + xyci = ci’(x’y+xy’) + ci (xy+x’y’) = ci’(x’y+xy’) + ci (x’y+xy’)’ = ci  (x  y) co = x’yci + xy’ci + xyci’ + xyci = ci (x’y+xy’) + xy(ci’+ci ) = ci (x  y) + xyxyscicoUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 5CMOS adderFor the carry, we can first use De Morgan’s lawsFor the xor , recall that a xor b = ab’ + a’b and (a xor b)’ = ab + a’b’Vddx’yOutxy’yx’ xy’xyscicocoxysciUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 6MultiplexorA multiplexor (selector or mux) selects one of n inputs to be outputLet’s make it easy and start with a 2-input muxwhen s = 0, f = awhen s = 1, f = babcdfs0s1abfsUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 72 input Multiplexor designs a b f0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1f = s’ab’ + s’ab + sa’b + sab = s’a(b’+b) + sb(a’+a) = s’a + sbbasfUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 8Making bigger muxesYou can design them directly, or just glue together smaller muxes:cdfs1abs0University of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 9DecodersDecode an n-bit input to set output line 2n-1ab11100100a b 00 01 10 110 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 100011011baUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 10Programmable Logic Array (PLA)Since all Boolean functions can be expressed in sum of products form, we can implement a set of n input functions systematically in hardware using a


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UT CS 310 - Combinational logic

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