University of Texas at Austin CS310 - Computer Organization Spring 2009 Don FussellCombinational LogicUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 2Multi-input gates - (x+(y*z))’yxOutVddz01100001010100111000x01110110z1010outyVery easy with inverting gatesUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 3Half Adder1-bit addition (x + y) outputs: sum s and carry c s = xy’ + x’y (x XOR y or x ⊕ y) c = xy1000c01110110y1000sxxyscUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 4Full 1-bit adderNeed a carry in ci101100100110101100111000x1000co11110110ci1000sy s = x’yci’+ xy’ci’ + x’y’ci + xyci = ci’(x’y+xy’) + ci (xy+x’y’) = ci’(x’y+xy’) + ci (x’y+xy’)’ = ci ⊕ (x ⊕ y) co = x’yci + xy’ci + xyci’ + xyci = ci (x’y+xy’) + xy(ci’+ci ) = ci (x ⊕ y) + xyxyscicoUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 5CMOS adderFor the carry, we can first use De Morgan’s lawsFor the xor, recall that a xor b = ab’ + a’b and (a xor b)’ = ab + a’b’Vddx’yOutxy’yx’ xy’xyscicocoxysciUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 6MultiplexorA multiplexor (selector or mux) selects one of ninputs to be outputLet’s make it easy and start with a 2-input muxwhen s = 0, f = awhen s = 1, f = babcdfs0s1abfsUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 72 input Multiplexor design11100001110100111000s11110110b0000faf = s’ab’ + s’ab + sa’b + sab = s’a(b’+b) + sb(a’+a) = s’a + sbbasfUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 8Making bigger muxesYou can design them directly, or just glue together smaller muxes:cdfs1abs0University of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 9DecodersDecode an n-bit input to set output line 2n-1ab1110010010001101001000100101100110b001000a00011011baUniversity of Texas at Austin CS310 - Computer Organization Spring 2009 Don Fussell 10Programmable Logic Array (PLA)Since all Boolean functions can be expressed in sum ofproducts form, we can implement a set of n input functionssystematically in hardware using a