I/O DevicesOverviewHardware or Software?DevicesSlide 5Device ControllerI/O ControllerI/O PortsMemory-Mapped I/O (1)Memory-Mapped I/O (2)3 Ways to Perform I/OPollingInterruptsHost-controller interface: InterruptsSupport for InterruptsInterrupt HandlerOther Types of InterruptsDirect Memory Access (DMA)DMA-CPU ProtocolDirect Memory Access (DMA)DMA IssuesDiscussionI/O Software LayersDevice DriversSlide 25Functions in Device DriversBufferingBuffering strategiesError ReportingQuizCopyright ©: Nahrstedt, Angrave, Abdelzaher 1I/O DevicesCopyright ©: Nahrstedt, Angrave, Abdelzaher2OverviewBasic I/O hardware ports, buses, devices and controllers I/O Software Interrupt Handlers, Device Driver, Device-Independent Software, User-Space I/O Software Important conceptsThree ways to perform I/O operationsPolling, interrupt and DMAsCopyright ©: Nahrstedt, Angrave, Abdelzaher3Hardware or Software?Is the following component software or hardware?Device controllerIs the following component software or hardware?Device driverCopyright ©: Nahrstedt, Angrave, Abdelzaher4DevicesDevicesStorage devices (disk, tapes)Transmission devices (network card, modem)Human interface devices (screen, keyboard, mouse)Specialized device (joystick)Copyright ©: Nahrstedt, Angrave, Abdelzaher5Copyright ©: Nahrstedt, Angrave, Abdelzaher6Device ControllerI/O units typically consist of A mechanical component: the device itselfAn electronic component: the device controller or adapter. Interface between controller and device is a very low level interface. Example: Disk controller converts the serial bit stream, coming off the drive into a block of bytes, and performs error correction.Copyright ©: Nahrstedt, Angrave, Abdelzaher7I/O ControllerDisk controller implements the disk side of the protocol that does: bad error mapping, prefetching, buffering, caching Controller has registers for data and control CPU and controllers communicate via I/O instructions and registers Memory-mapped I/OCopyright ©: Nahrstedt, Angrave, Abdelzaher8I/O Ports 4 registers - status, control, data-in, data-outStatus - states whether the current command is completed, byte is available, device has an error, etc Control - host determines to start a command or change the mode of a device Data-in - host reads to get input Data-out - host writes to send output Size of registers - 1 to 4 bytesCopyright ©: Nahrstedt, Angrave, Abdelzaher9Memory-Mapped I/O (1)(a) Separate I/O and memory space(b) Memory-mapped I/O(c) HybridCopyright ©: Nahrstedt, Angrave, Abdelzaher10Memory-Mapped I/O (2)(a) A single-bus architecture(b) A dual-bus memory architectureCopyright ©: Nahrstedt, Angrave, Abdelzaher113 Ways to Perform I/OPollingInterruptDMACopyright ©: Nahrstedt, Angrave, Abdelzaher12Polling Polling - use CPU to Busy wait and watch status bits Feed data into a controller register 1 byte at a timeEXPENSIVE for large transfers Not acceptable except small dedicated systems not running multiple processesCopyright ©: Nahrstedt, Angrave, Abdelzaher13InterruptsConnections between devices and interrupt controller actually use interrupt lines on the bus rather than dedicated wiresCopyright ©: Nahrstedt, Angrave, Abdelzaher14Host-controller interface: Interrupts CPU hardware has the interrupt report line that the CPU senses after executing every instruction device raises an interrupt CPU catches the interrupt and saves the state (e.g., Instruction pointer) CPU dispatches the interrupt handler interrupt handler determines cause, services the device and clears the interrupt Why interrupts?Real life analogy for interruptAn alarm sets off when the food/laundry is readySo you can do other things in betweenCopyright ©: Nahrstedt, Angrave, Abdelzaher15Support for InterruptsNeed the ability to defer interrupt handling during critical processing Need efficient way to dispatch the proper device Interrupt comes with an address (offset in interrupt vector) that selects a specific interrupt handling Need multilevel interrupts - interrupt priority levelCopyright ©: Nahrstedt, Angrave, Abdelzaher16Interrupt HandlerAt boot time, OS probes the hardware buses to determine what devices are present install corresponding interrupt handlers into the interrupt vector During I/O interrupt, controller signals that device is readyCopyright ©: Nahrstedt, Angrave, Abdelzaher17Other Types of InterruptsInterrupt mechanisms are used to handle wide variety of exceptions: Division by zero, wrong address Virtual memory paging System calls (software interrupts/signals, trap)Copyright ©: Nahrstedt, Angrave, Abdelzaher18Direct Memory Access (DMA) Direct memory access (DMA) Assists in exchange of data between CPU and I/O controllerCPU can request data from I/O controller byte by byte – but this might be inefficient (e.g. for disk data transfer)Uses a special purpose processor, called a DMA controllerCopyright ©: Nahrstedt, Angrave, Abdelzaher19DMA-CPU ProtocolUse disk DMA as an exampleCPU programs DMA controller, sets registers to specify source/destination addresses, byte count and control information (e.g., read/write) and goes on with other work DMA controller proceeds to operate the memory bus directly without help of main CPU – request from I/O controller to move data to memory Disk controller transfers data to main memoryDisk controller acks transfer to DMA controllerCopyright ©: Nahrstedt, Angrave, Abdelzaher20Direct Memory Access (DMA)Operation of a DMA transferCopyright ©: Nahrstedt, Angrave, Abdelzaher21DMA IssuesHandshaking between DMA controller and the device controller Cycle stealing DMA controller takes away CPU cycles when it uses CPU memory bus, hence blocks the CPU from accessing the memory In general DMA controller improves the total system performanceCopyright ©: Nahrstedt, Angrave, Abdelzaher22DiscussionTradeoffs betweenProgrammed I/OInterrupt-driven I/OI/O using DMAWhich one is the fastest for a single I/O request?Which one gives the highest throughput?Copyright ©: Nahrstedt, Angrave, Abdelzaher23I/O Software LayersLayers of the I/O Software SystemCopyright ©: Nahrstedt, Angrave, Abdelzaher24Device DriversLogical position of device drivers is shown hereCommunications between drivers and device controllers goes over the
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