1Copyright ©: Nahrstedt, Angrave, Abdelzaher 1I/O Devices Copyright ©: Nahrstedt, Angrave, Abdelzaher2Overview Basic I/O hardware ports, buses, devices and controllers I/O Software Interrupt Handlers, Device Driver, Device-Independent Software, User-Space I/O Software Important concepts Three ways to perform I/O operations Polling, interrupt and DMAs2Copyright ©: Nahrstedt, Angrave, Abdelzaher3Hardware or Software? Is the following component software or hardware? Device controller Is the following component software or hardware? Device driverCopyright ©: Nahrstedt, Angrave, Abdelzaher4Devices Devices Storage devices (disk, tapes) Transmission devices (network card, modem) Human interface devices (screen, keyboard, mouse) Specialized device (joystick)3Copyright ©: Nahrstedt, Angrave, Abdelzaher5Copyright ©: Nahrstedt, Angrave, Abdelzaher6Device Controller I/O units typically consist of A mechanical component: the device itself An electronic component: the device controller or adapter. Interface between controller and device is a very low level interface. Example: Disk controller converts the serial bit stream, coming off the drive into a block of bytes, and performs error correction.4Copyright ©: Nahrstedt, Angrave, Abdelzaher7I/O ControllerDisk controller implements the disk side of the protocol that does: bad error mapping, prefetching, buffering, caching Controller has registers for data and control CPU and controllers communicate via I/O instructions and registers Memory-mapped I/O Copyright ©: Nahrstedt, Angrave, Abdelzaher8I/O Ports 4 registers - status, control, data-in, data-out Status - states whether the current command is completed, byte is available, device has an error, etc Control - host determines to start a command or change the mode of a device Data-in - host reads to get input Data-out - host writes to send output Size of registers - 1 to 4 bytes5Copyright ©: Nahrstedt, Angrave, Abdelzaher9Memory-Mapped I/O (1)(a) Separate I/O and memory space(b) Memory-mapped I/O(c) HybridCopyright ©: Nahrstedt, Angrave, Abdelzaher10Memory-Mapped I/O (2)(a) A single-bus architecture(b) A dual-bus memory architecture6Copyright ©: Nahrstedt, Angrave, Abdelzaher113 Ways to Perform I/O Polling Interrupt DMACopyright ©: Nahrstedt, Angrave, Abdelzaher12Polling Polling - use CPU to Busy wait and watch status bits Feed data into a controller register 1 byte at a time EXPENSIVE for large transfers Not acceptable except small dedicated systems not running multiple processes7Copyright ©: Nahrstedt, Angrave, Abdelzaher13Interrupts Connections between devices and interrupt controller actually use interrupt lines on the bus rather than dedicated wiresCopyright ©: Nahrstedt, Angrave, Abdelzaher14Host-controller interface: Interrupts CPU hardware has the interrupt report line that the CPU senses after executing every instruction device raises an interrupt CPU catches the interrupt and saves the state (e.g., Instruction pointer) CPU dispatches the interrupt handler interrupt handler determines cause, services the device and clears the interrupt Why interrupts? Real life analogy for interrupt An alarm sets off when the food/laundry is ready So you can do other things in between8Copyright ©: Nahrstedt, Angrave, Abdelzaher15Support for Interrupts Need the ability to defer interrupt handling during critical processing Need efficient way to dispatch the proper device Interrupt comes with an address (offset in interrupt vector) that selects a specific interrupt handling Need multilevel interrupts - interrupt priority level Copyright ©: Nahrstedt, Angrave, Abdelzaher16Interrupt Handler At boot time, OS probes the hardware buses to determine what devices are present install corresponding interrupt handlers into the interrupt vector During I/O interrupt, controller signals that device is ready9Copyright ©: Nahrstedt, Angrave, Abdelzaher17Other Types of Interrupts Interrupt mechanisms are used to handle wide variety of exceptions: Division by zero, wrong address Virtual memory paging System calls (software interrupts/signals, trap) Multi-threaded systemsCopyright ©: Nahrstedt, Angrave, Abdelzaher18Direct Memory Access (DMA) Direct memory access (DMA) Assists in exchange of data between CPU and I/O controller CPU can request data from I/O controller byte by byte – but this might be inefficient (e.g. for disk data transfer) Uses a special purpose processor, called a DMA controller Real life analogy Hire a helper---housekeeper10Copyright ©: Nahrstedt, Angrave, Abdelzaher19DMA-CPU Protocol Use disk DMA as an example CPU programs DMA controller, sets registers to specify source/destination addresses, byte count and control information (e.g., read/write) and goes on with other work DMA controller proceeds to operate the memory bus directly without help of main CPU – request from I/O controller to move data to memory Disk controller transfers data to main memory Disk controller acks transfer to DMA controllerCopyright ©: Nahrstedt, Angrave, Abdelzaher20Direct Memory Access (DMA) Operation of a DMA transfer11Copyright ©: Nahrstedt, Angrave, Abdelzaher21DMA Issues Handshaking between DMA controller and the device controller Cycle stealing DMA controller takes away CPU cycles when it uses CPU memory bus, hence blocks the CPU from accessing the memory In general DMA controller improves the total system performance Copyright ©: Nahrstedt, Angrave, Abdelzaher22Discussion Tradeoffs between Programmed I/O Interrupt-driven I/O I/O using DMA Which one is the fastest for a single I/O request? Which one gives the highest throughput?12Copyright ©: Nahrstedt, Angrave, Abdelzaher23I/O Software Layers Layers of the I/O Software SystemCopyright ©: Nahrstedt, Angrave, Abdelzaher24Device Drivers Logical position of device drivers is shown here Communications between drivers and device controllers goes over the bus13Copyright ©: Nahrstedt, Angrave, Abdelzaher25Device Drivers Device-specific code to control an IO device, is usually written by device's manufacturer Each controller has some device registers used to give it commands. The number of device registers and the nature of commands vary
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