CS 501: Software EngineeringAdministrationPerformance of Computer SystemsPerformance ChallengesUnderstand the Interactions between Hardware and SoftwareSlide 6Understand Interactions between Hardware and SoftwareLook for BottlenecksTimescalePredicting System PerformanceLook for Bottlenecks: UtilizationMathematical ModelsMathematical Models: QueuesQueuesBehavior of Queues: UtilizationMeasurements on Operational SystemsExample: Web LaboratoryTechniques: SimulationCase Study: Performance of Disk ArraySlide 20Fixing Bad PerformanceTechniques for Eliminating BottlenecksPredicting Performance Change: Moore's LawMoore's Law: Rules of ThumbMoore's Law and System DesignMoore's Law ExampleParkinson's LawFalse Assumptions from the PastMoore's Law and the Long TermSlide 301CS 501 Spring 2006CS 501: Software EngineeringLecture 22Performance of Computer Systems2CS 501 Spring 2006Administration3CS 501 Spring 2006Performance of Computer SystemsIn most computer systemsThe cost of people is much greater than the cost of hardwareYet performance is importantFuture loads may be much greater than predictedA single bottleneck can slow down an entire system4CS 501 Spring 2006Performance ChallengesTasks• Predict performance problems before a system is implemented• Identify causes and fix problems after a system is implementedBasic techniques• Understand how the underlying hardware and networking components interact when executing the system• Calculate the capacity and load on each component• Identify components that are approaching peak capacity5CS 501 Spring 2006Understand the Interactions between Hardware and SoftwareExample: execution of http://www.cs.cornell.edu/Client Serversdomain name serviceTCP connectionHTTP get6CS 501 Spring 2006Understand the Interactions between Hardware and Software:Thread :Toolkit :ComponentPeer target:HelloWorldrunrun callbackLoophandleExposepaint7CS 501 Spring 2006DecompressStream audioStream videoforkjoinstart statestop stateUnderstand Interactions between Hardware and Software8CS 501 Spring 2006Look for BottlenecksPossible areas of congestionNetwork loadDatabase accesshow many joins to build a record?Locks and sequential processingCPU performance is rarely a factor, except in mathematical algorithms. More likely bottlenecks are:Reading data from disk (including paging)Moving data from memory to CPU9CS 501 Spring 2006TimescaleOperations per secondCPU instruction: 1,000,000,000Disk latency: 60 read: 25,000,000 bytesNetwork LAN: 10,000,000 bytesdial-up modem: 6,000 bytes10CS 501 Spring 2006Predicting System Performance• Direct measurement on subsystem (benchmark)• Mathematical models• Simulation• Rules of thumbAll require detailed understanding of the interaction between software and hardware systems.11CS 501 Spring 2006Look for Bottlenecks: Utilizationutilization = mean service timemean inter-arrival timeWhen the utilization of any hardware component exceeds 30%, be prepared for congestion.Peak loads and temporary increases in demand can be much greater than the average.Utilization is the proportion of the capacity of a service that is used on average.12CS 501 Spring 2006Mathematical ModelsQueueing theoryGood estimates of congestion can be made for single-server queues with: • arrivals that are independent, random events (Poisson process)• service times that follow families of distributions (e.g., negative exponential, gamma)Many of the results can be extended to multi-server queues.13CS 501 Spring 2006Mathematical Models: Queuesarrive wait in line service departSingle server queue14CS 501 Spring 2006Queuesarrive wait in lineservicedepartMulti-server queue15CS 501 Spring 2006Behavior of Queues: Utilizationmeandelayutilization1016CS 501 Spring 2006Measurements on Operational Systems• Benchmarks: Run system on standard problem sets, sample inputs, or a simulated load on the system.• Instrumentation: Clock specific events.If you have any doubt about the performance of part of a system, experiment with a simulated load.17CS 501 Spring 2006Example: Web LaboratoryBenchmark: Throughput v. number of CPUstotal MB/saverage / CPU18CS 501 Spring 2006Techniques: SimulationModel the system as set of states and eventsadvance simulated time determine which events occurred update state and event listrepeatDiscrete time simulation: Time is advanced in fixed steps (e.g., 1 millisecond)Next event simulation: Time is advanced to next eventEvents can be simulated by random variables (e.g., arrival of next customer, completion of disk latency)19CS 501 Spring 2006Case Study: Performance of Disk ArrayWhen many transaction use a disk array, each transaction must:wait for specific disk platterwait for I/O channelsignal to move heads on disk platterwait for I/O channelpause for disk rotationread dataClose agreement between: results from queuing theory, simulation, and direct measurement (within 15%).20CS 501 Spring 2006Example: Web LaboratoryBalance of ResourcesIdeal RealisticNetworking 500 Mbit/sec 100 Mbit/secData online all few crawls/yearMetadata online all all?Disk 750 TB 240 TBTape archive all few crawls/yearComputers research sharedseparate with storage21CS 501 Spring 2006Fixing Bad PerformanceIf a system performs badly, begin by identifying the cause:• Instrumentation. Add timers to the code. Often this will reveal that the delays are centered in one specific part of the system.• Test loads. Run the system with varying loads, e.g., high transaction rates, large input files, many users, etc. This may reveal the characteristics of when the system runs badly.• Design and code reviews. Have a team review the system design and suspect sections of code for performance problems. This may reveal an algorithm that is running very slowly, e.g., a sort, locking procedure, etc.Fix the underlying cause or the problem will return!22CS 501 Spring 2006Techniques for Eliminating BottlenecksSerial and Parallel ProcessingSingle thread v. multi-threade.g., Unix forkGranularity of locks on datae.g., record lockingNetwork congestione.g., back-off algorithms23CS 501 Spring 2006Predicting Performance Change:Moore's LawOriginal version: The density of transistors in an integrated circuit will double every year. (Gordon Moore, Intel, 1965) Current version:Cost/performance of silicon chips doubles every 18 months.24CS 501 Spring 2006Moore's Law: Rules of
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