1CSE 120CSE 120Principles of Operating Principles of Operating SystemsSystemsFall 2002Fall 2002Lecture 10: PagingLecture 10: PagingGeoffrey M. VoelkerGeoffrey M. VoelkerNovember 6, 2002 CSE 120 – Lecture 10 – Paging 2© 2002 Geoffrey M. VoelkerLecture OverviewLecture OverviewToday we’ll cover more paging mechanisms:z OptimizationsX Managing page tables (space)X Efficient translations (TLBs) (time)X Demand paged virtual memory (space)z Recap address translationz Advanced FunctionalityX Sharing memoryX Copy on WriteX Mapped files2November 6, 2002 CSE 120 – Lecture 10 – Paging 3© 2002 Geoffrey M. VoelkerManaging Page TablesManaging Page Tablesz Last lecture we computed the size of the page table for a 32-bit address space w/ 4K pages to be 4MBX This is far far too much overhead for each processz How can we reduce this overhead?X Observation: Only need to map the portion of the address space actually being used (tiny fraction of entire addr space)z How do we only map what is being used?X Can dynamically extend page table…X Does not work if addr space is sparce (internal fragmentation)z Use another level of indirection: two-level page tablesNovember 6, 2002 CSE 120 – Lecture 10 – Paging 4© 2002 Geoffrey M. VoelkerTwoTwo--Level Page TablesLevel Page Tablesz Two-level page tablesX Virtual addresses (VAs) have three parts:» Master page number, secondary page number, and offsetX Master page table maps VAs to secondary page tableX Secondary page table maps page number to physical pageX Offset indicates where in physical page address is locatedz ExampleX 4K pages, 4 bytes/PTEX How many bits in offset? 4K = 12 bitsX Want master page table in one page: 4K/4 bytes = 1K entriesX Hence, 1K secondary page tables. How many bits?X Master (1K) = 10, offset = 12, inner = 32 – 10 – 12 = 20 bits3November 6, 2002 CSE 120 – Lecture 10 – Paging 5© 2002 Geoffrey M. VoelkerTwoTwo--Level Page TablesLevel Page TablesPage tableMaster page number SecondaryVirtual AddressMaster Page TablePage frame OffsetPhysical AddressPhysical MemoryOffsetPage frameSecondary Page TableNovember 6, 2002 CSE 120 – Lecture 10 – Paging 6© 2002 Geoffrey M. VoelkerAddressing Page TablesAddressing Page TablesWhere do we store page tables (which address space)?z Physical memoryX Easy to address, no translation requiredX But, allocated page tables consume memory for lifetime of VASz Virtual memory (OS virtual address space)X Cold (unused) page table pages can be paged out to diskX But, addressing page tables requires translationX How do we stop recursion?X Do not page the outer page table (called wiring)z If we’re going to page the page tables, might as well page the entire OS address space, tooX Need to wire special code and data (fault, interrupt handlers)4November 6, 2002 CSE 120 – Lecture 10 – Paging 7© 2002 Geoffrey M. VoelkerEfficient TranslationsEfficient Translationsz Our original page table scheme already doubled the cost of doing memory lookupsX One lookup into the page table, another to fetch the dataz Now two-level page tables triple the cost!X Two lookups into the page tables, a third to fetch the dataX And this assumes the page table is in memoryz How can we use paging but also have lookups cost about the same as fetching from memory?X Cache translations in hardwareX Translation Lookaside Buffer (TLB)X TLB managed by Memory Management Unit (MMU)November 6, 2002 CSE 120 – Lecture 10 – Paging 8© 2002 Geoffrey M. VoelkerTLBsTLBsz Translation Lookaside BuffersX Translate virtual page #s into PTEs (not physical addrs)X Can be done in a single machine cyclez TLBs implemented in hardwareX Fully associative cache (all entries looked up in parallel)X Cache tags are virtual page numbersX Cache values are PTEs (entries from page tables)X With PTE + offset, can directly calculate physical addressz TLBs exploit localityX Processes only use a handful of pages at a time» 16-48 entries/pages (64-192K)» Only need those pages to be “mapped”X Hit rates are therefore very important5November 6, 2002 CSE 120 – Lecture 10 – Paging 9© 2002 Geoffrey M. VoelkerManaging Managing TLBsTLBsz Address translations for most instructions are handled using the TLBX >99% of translations, but there are misses (TLB miss)…z Who places translations into the TLB (loads the TLB)?X Hardware (Memory Management Unit)» Knows where page tables are in main memory» OS maintains tables, HW accesses them directly» Tables have to be in HW-defined format (inflexible)X Software loaded TLB (OS)» TLB faults to the OS, OS finds appropriate PTE, loads it in TLB» Must be fast (but still 20-200 cycles)» CPU ISA has instructions for manipulating TLB» Tables can be in any format convenient for OS (flexible)November 6, 2002 CSE 120 – Lecture 10 – Paging 10© 2002 Geoffrey M. VoelkerManaging Managing TLBsTLBs(2)(2)z OS ensures that TLB and page tables are consistentX When it changes the protection bits of a PTE, it needs to invalidate the PTE if it is in the TLBz Reload TLB on a process context switchX Invalidate all entriesX Why? What is one way to fix it?z When the TLB misses and a new PTE has to be loaded, a cached PTE must be evictedX Choosing PTE to evict is called the TLB replacement policyX Implemented in hardware, often simple (e.g., Last-Not-Used)6November 6, 2002 CSE 120 – Lecture 10 – Paging 11© 2002 Geoffrey M. VoelkerPaged Virtual MemoryPaged Virtual Memoryz We’ve mentioned before that pages can be moved between memory and diskX This process is called demand pagingz OS uses main memory as a page cache of all the data allocated by processes in the systemX Initially, pages are allocated from memoryX When memory fills up, allocating a page in memory requires some other page to be evicted from memory» Why physical memory pages are called “frames”X Evicted pages go to disk (where? the swap file)X The movement of pages between memory and disk is done by the OS, and is transparent to the applicationNovember 6, 2002 CSE 120 – Lecture 10 – Paging 12© 2002 Geoffrey M. VoelkerPage FaultsPage Faultsz What happens when a process accesses a page that has been evicted?1. When it evicts a page, the OS sets the PTE as invalid and stores the location of the page in the swap file in the PTE2. When a process accesses the page, the invalid PTE will cause a trap (page fault)3. The trap will run the OS page fault handler4. Handler uses the invalid PTE to locate page in swap file5. Reads page into a physical
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