Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 211Lecture 15: PCM, Networks• Today: PCM wrap-up, projects discussion, on-chip networks background2Hard Error Tolerance in PCM• PCM cells will eventually fail; important to cause gradual capacity degradation when this happens• Pairing: among the pool of faulty pages, pair two pages that have faults in different locations; replicate data across the two pages Ipek et al., ASPLOS’10• Errors are detected with parity bits; replica reads are issued if the initial read is faulty3ECP Schechter et al., ISCA’10• Instead of using ECC to handle a few transient faults in DRAM, use error-correcting pointers to handle hard errors in specific locations• For a 512-bit line with 1 failed bit, maintain a 9-bit field to track the failed location and another bit to store the value in that location• Can store multiple such pointers and can recover from faults in the pointers too• ECC has similar storage overhead and can handle soft errors; but ECC has high entropy and can hasten wearout4SAFER Seong et al., MICRO 2010• Most PCM hard errors are stuck-at faults (stuck at 0 or stuck at 1)• Either write the word or its flipped version so that the failed bit is made to store the stuck-at value• For multi-bit errors, the line can be partitioned such that each partition has a single error• Errors are detected by verifying a write; recently failed bit locations are cached so multiple writes can be avoided5FREE-p Yoon et al., HPCA 2011• When a PCM block is unusable because the number of hard errors has exceeded the ECC capability, it is remapped to another address; the pointer to this address is stored in the failed block• The pointer can be replicated many times in the failed block to tolerate the multiple errors in the failed block• Requires two accesses when handling failed blocks; this overhead can be reduced by caching the pointer at the memory controller6Interconnection Networks• Recall: fully connected network, arrays/rings, meshes/tori, trees, butterflies, hypercubes• Consider a k-ary d-cube: a d-dimension array with k elements in each dimension, there are links between elements that differ in one dimension by 1 (mod k)• Number of nodes N = kdNumber of switches :Switch degree :Number of links :Pins per node :Avg. routing distance:Diameter :Bisection bandwidth :Switch complexity :N2d + 1Nd2wdd(k-1)/2d(k-1)2wkd-1Should we minimize or maximize dimension?(2d + 1)2(with no wraparound)7Routing• Deterministic routing: given the source and destination, there exists a unique route• Adaptive routing: a switch may alter the route in order to deal with unexpected events (faults, congestion) – more complexity in the router vs. potentially better performance• Example of deterministic routing: dimension order routing: send packet along first dimension until destination co-ord (in that dimension) is reached, then next dimension, etc.8Deadlock ExamplePackets of message 1Packets of message 2Packets of message 3Packets of message 44-way switchOutput portsEach message is attempting to make a left turn – it must acquire anoutput port, while still holding on to a series of input and output portsInput ports9Deadlock-Free Proofs• Number edges and show that all routes will traverse edges in increasing (or decreasing) order – therefore, it will be impossible to have cyclic dependencies• Example: k-ary 2-d array with dimension routing: first route along x-dimension, then along y1 2 32 1 01 2 32 1 01 2 32 1 01 2 32 1 017181918171610Breaking Deadlock II• Consider the eight possible turns in a 2-d array (note that turns lead to cycles)• By preventing just two turns, cycles can be eliminated• Dimension-order routing disallows four turns• Helps avoid deadlock even in adaptive routingWest-First North-Last Negative-First Can allowdeadlocks11Deadlock Avoidance with VCs• VCs provide another way to number the links such that a route always uses ascending link numbers2 1 01 2 32 1 01 2 32 1 01 2 32 1 0171819181716102 101 100101 102 103117118119118117116202 201 200201 202 203217218219218217216• Alternatively, use West-first routing on the 1st plane and cross over to the 2nd plane in case you need to go West again (the 2nd plane uses North-last, for example)12Packets/Flits• A message is broken into multiple packets (each packet has header information that allows the receiver to re-construct the original message)• A packet may itself be broken into flits – flits do not contain additional headers• Two packets can follow different paths to the destination Flits are always ordered and follow the same path• Such an architecture allows the use of a large packet size (low header overhead) and yet allows fine-grained resource allocation on a per-flit basis13Flow Control• The routing of a message requires allocation of various resources: the channel (or link), buffers, control state• Bufferless: flits are dropped if there is contention for a link, NACKs are sent back, and the original sender has to re-transmit the packet• Circuit switching: a request is first sent to reserve the channels, the request may be held at an intermediate router until the channel is available (hence, not truly bufferless), ACKs are sent back, and subsequent packets/flits are routed with little effort (good for bulk transfers)14Buffered Flow Control• A buffer between two channels decouples the resource allocation for each channel – buffer storage is not as precious a resource as the channel (perhaps, not so true for on-chip networks)• Packet-buffer flow control: channels and buffers are allocated per packet Store-and-forward Cut-throughTime-Space diagramsH B B B TH B B B TH B B B T0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CycleChannel0123ChannelH B B B TH B B B TH B B B T012315Flit-Buffer Flow Control (Wormhole)• Wormhole Flow Control: just like cut-through, but with buffers allocated per flit (not channel)• A head flit must acquire three resources at the next switch before being forwarded: channel control state (virtual channel, one per input port) one flit buffer one flit of channel bandwidth The other flits adopt the same virtual channel as the head and only compete