Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 321Lecture 13: Interconnection Networks• Topics: lots of background, recent innovations for power and performance2Interconnection Networks• Recall: fully connected network, arrays/rings, meshes/tori, trees, butterflies, hypercubes• Consider a k-ary d-cube: a d-dimension array with k elements in each dimension, there are links between elements that differ in one dimension by 1 (mod k)• Number of nodes N = kdNumber of switches :Switch degree :Number of links :Pins per node :Avg. routing distance:Diameter :Bisection bandwidth :Switch complexity :N2d + 1Nd2wdd(k-1)/2d(k-1)2wkd-1Should we minimize or maximize dimension?(2d + 1)2(with no wraparound)3Routing• Deterministic routing: given the source and destination, there exists a unique route• Adaptive routing: a switch may alter the route in order to deal with unexpected events (faults, congestion) – more complexity in the router vs. potentially better performance• Example of deterministic routing: dimension order routing: send packet along first dimension until destination co-ord (in that dimension) is reached, then next dimension, etc.4Deadlock ExamplePackets of message 1Packets of message 2Packets of message 3Packets of message 44-way switchOutput portsEach message is attempting to make a left turn – it must acquire anoutput port, while still holding on to a series of input and output portsInput ports5Deadlock-Free Proofs• Number edges and show that all routes will traverse edges in increasing (or decreasing) order – therefore, it will be impossible to have cyclic dependencies• Example: k-ary 2-d array with dimension routing: first route along x-dimension, then along y1 2 32 1 01 2 32 1 01 2 32 1 01 2 32 1 01718191817166Breaking Deadlock II• Consider the eight possible turns in a 2-d array (note that turns lead to cycles)• By preventing just two turns, cycles can be eliminated• Dimension-order routing disallows four turns• Helps avoid deadlock even in adaptive routingWest-First North-Last Negative-First Can allowdeadlocks7Deadlock Avoidance with VCs• VCs provide another way to number the links such that a route always uses ascending link numbers2 1 01 2 32 1 01 2 32 1 01 2 32 1 0171819181716102 101 100101 102 103117118119118117116202 201 200201 202 203217218219218217216• Alternatively, use West-first routing on the 1st plane and cross over to the 2nd plane in case you need to go West again (the 2nd plane uses North-last, for example)8Packets/Flits• A message is broken into multiple packets (each packet has header information that allows the receiver to re-construct the original message)• A packet may itself be broken into flits – flits do not contain additional headers• Two packets can follow different paths to the destination Flits are always ordered and follow the same path• Such an architecture allows the use of a large packet size (low header overhead) and yet allows fine-grained resource allocation on a per-flit basis9Flow Control• The routing of a message requires allocation of various resources: the channel (or link), buffers, control state• Bufferless: flits are dropped if there is contention for a link, NACKs are sent back, and the original sender has to re-transmit the packet• Circuit switching: a request is first sent to reserve the channels, the request may be held at an intermediate router until the channel is available (hence, not truly bufferless), ACKs are sent back, and subsequent packets/flits are routed with little effort (good for bulk transfers)10Buffered Flow Control• A buffer between two channels decouples the resource allocation for each channel – buffer storage is not as precious a resource as the channel (perhaps, not so true for on-chip networks)• Packet-buffer flow control: channels and buffers are allocated per packet Store-and-forward Cut-throughTime-Space diagramsH B B B TH B B B TH B B B T0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CycleChannel0123ChannelH B B B TH B B B TH B B B T012311Flit-Buffer Flow Control (Wormhole)• Wormhole Flow Control: just like cut-through, but with buffers allocated per flit (not channel)• A head flit must acquire three resources at the next switch before being forwarded: channel control state (virtual channel, one per input port) one flit buffer one flit of channel bandwidth The other flits adopt the same virtual channel as the head and only compete for the buffer and physical channel Consumes much less buffer space than cut-through routing – does not improve channel utilization as another packet cannot cut in (only one VC per input port)12Virtual Channel Flow Control• Each switch has multiple virtual channels per phys. channel• Each virtual channel keeps track of the output channel assigned to the head, and pointers to buffered packets• A head flit must allocate the same three resources in the next switch before being forwarded• By having multiple virtual channels per physical channel, two different packets are allowed to utilize the channel and not waste the resource when one packet is idle13Example• Wormhole:• Virtual channel:ABBA is going from Node-1 to Node-4; B is going from Node-0 to Node-5Node-1Node-0Node-5(blocked, no free VCs/buffers)Node-2 Node-3 Node-4idleidleABANode-1Node-0Node-5(blocked, no free VCs/buffers)Node-2 Node-3 Node-4BATraffic Analogy: B is trying to make a left turn; A is trying to go straight; there is no left-only lane with wormhole, but there is one with VC14Buffer Management• Credit-based: keep track of the number of free buffers in the downstream node; the downstream node sends back signals to increment the count when a buffer is freed; need enough buffers to hide the round-trip latency• On/Off: the upstream node sends back a signal when its buffers are close to being full – reduces upstream signaling and counters, but can waste buffer space15Router Pipeline• Four typical stages: RC routing computation: the head flit indicates the VC that it belongs to, the VC state is updated, the headers are examined and the next output channel is computed (note: this is done for all the head flits