 Y0 Y1 C Y2 B Y3 A Y4 Y5 Y6 E Y73-line to 8-line DecoderY0m0Y1m1Y2m2Y3m3Y4m4Y5m5Y6m6Y7m7E8-line to 1-line MUX:D0D1D2D3D4D5D6D7m0m1m2m3m4m5m6m7EYW D0  D1  D2  D3 Y D4  D5 W D6  D7 EC B AROM NMOS Decoder+5V+5V+5VA2A1A0Y1Y0Y2ROM NMOS Encoder+5VY1Y0Y2D0D1D2D3EPROM Encoder w/ Floating Gates+5VY1Y0(-)(-)(-)(-)(-)(-)Y2D0D1D2D32 x 8 PLD AND Array ExamplesAND:OR:NAND:NOR:I4I3I2I1I4I3I2I1I4I3I2I1----XOR:RAM NMOS EncoderY1Y0Y2D0D1D2D3WE+++ +++RAM Chip AddressingStraight Decoding:2D Decoding:2D Decoding with Banks:A0A1A2A3A4A5A6A7A9A10A11A12A13D0D1D2D3D4D5D6D7WEA0A1A2A3A4A5A6A7A9A10A11A12A13RASCASD0D1D2D3D4D5D6D7WEA0A1A2A3A4A5A6A7A9A10A11A12A13Bank 0Bank 1RASCASD0D1D2D3D4D5D6D7WEIn2Clock WaveForm Illustrations1 2 3 n n+1t1 t2 t3 tn tn+1ClockInputsInputsOutputsClockn n+1Qn Stable Qn->Qn+1 Qn+1 StableOutputsIn1QQ_MEMORYELEMENTSSequential Logic Circuit Block DiagramINPUTLOGICBLOCKOUTPUTLOGICBLOCKInputsState FeedbackPresentStateOutputsSequential Logic Circuit ClassesMEMORYELEMENTSINPUTLOGICBLOCKOUTPUTLOGICBLOCKState FeedbackXYnZClass A SLC: Z = f(X, Y)MEMORYELEMENTSINPUTLOGICBLOCKOUTPUTLOGICBLOCKState FeedbackXYnZClass B SLC: Z = f(Y)MEMORYELEMENTSINPUTLOGICBLOCKState FeedbackXYn= ZClass C SLC: Z = YState Diagrams and TablesState Diagram:State Table:YnabPresent State Yn = aNext State Yn+1 = bX2/ Z2ZXX1/ Z1Yn+1 a Z1X1 a a Z2X2 bPS OutIn NSNo ChangeAdvance to bKQ_Q JKQ_Q JKQ_Q JKQ_Q JQ_Q DQ_Q DQ_Q DQ_Q DKQ_Q JKQ_Q JKQ_Q JKQ_Q J11KQ_Q J11KQ_Q J11KQ_Q J11KQ_Q J11Important Types of SLCsData Register:Shift Register:Synchronous Counter:Ripple