Laboratory FourAdder Logic Design PrincipalsConcepts:1. A Full Adder (FA), capable of adding two 1-bit operandsplus a carry bit, may be synthesized from a set of mintermsdefined by a truth table. This is 1-bit addition2. n-bit addition may be performed by cascading n FAs. Theresulting recursive circuit has many levels of logic and isslow, because each stage depends upon the previous stage.3. Two level n-bit non-recursive adders (consisting of only twolevels of logic) may be derived from cascaded adders byexpanding out the recursive equations, but are overlycomplex.4. Faster carry lookahead adder designs combine recursivesum computation with non-recursive carry propagation.Task One: Logic Design of a Ripple Adder. (5 pts) Suggested reading assignment: 5.10.1-5.10.21. (Pre) Record in your lab notebook the truth table to the fulladder, having inputs A, B, Cin and outputs S and Cout.2. (Pre) Write expressions for S and Cout as a sum of minterms.3. (Pre) Simplify Cout to minimal SOP form by employingBoolean algebra and record the results in your notebook.4. (Pre) It turns out that S cannot be simplified further in SOPform. However, you may use Boolean algebra to rewrite Sconcisely in terms of nested XOR operations, using thesymbol ⊕. Apply the relationship x ⊕ y = xy’ + x’y severaltimes to reduce your expression for S in Step 2 to S = A ⊕ B⊕ Cin.5. (Bonus Pre: 3 extra pts) Using the software in the back ofyour textbook, define a new project titled with your name(we will call it project) and enter the logic circuits for S andCout into Xilinx's Schematic Editor. Next, copy and pastetwo more full adders vertically down. Rename the inputs asAi, Bi, Ci and outputs as Si and Ci+1, 0 ≤ i ≤ 2, and connectthe stages with the "Ci" (set C0 to 0 and C3 will form afourth sum output). You should now have 10 non-zeroterminal (pin) signals total. Print your schematic, showingthe project name (your name). [Check with your labinstructor if you need help with this.]6. (Bonus Pre: 2 extra pts) Employ the Functional Simulationsoftware at home and define a signal waveform file titledwith your name for your three-bit ripple adder. Print thebeginning portion of your signal waveform and submit thesematerials as well as the schematic of Step 5 to your labinstructor.Task Two: Three-bit Two Level Adder (5 pts)1. (Pre) From the discussion of Task One, it can be seen thatthe expression for the sum output of a full adder havinginputs Ai, Bi, Ci and outputs Si and Ci+1, is Si = Ai ⊕ Bi ⊕ Ci,where i ≥ 0. Derive now the corresponding recursiveexpression for Ci+1, and write it in your lab notebook.2. (Pre) Consider a 3-bit adder employing three FA stages,with 0 ≤ i ≤ 2 and C0 = 0, such as described in Step 1.Derive non-recursive SOP (two level) expressions for Siand Ci+1, which only depend upon the Ai and Bi variables.[You do this by expanding out the recursive equations -- bysubstituting the expression for C1 into the equations for S1,and S2, and repeating this also for C2 and C3.] The resultingcircuit equations are faster than the ripple stage design ofTask One, because they involve only two levels of logic(i.e. a SOP design), but at the same time greatly increase incomplexity.3. It would be very cumbersome to implement a schematic forthe expressions derived in Step 2. Your instructor will nowillustrate an alternative design entry method, using theABEL language, that is available in the Xilinx FoundationSoftware, which can directly input the design equations forSi and Ci+1.4. Employ the Functional Simulation software and generatewaveforms for all 10 signals. Based upon these simulationresults, record an experimental truth table for your ABEL-based 3-bit adder design in your notebook. The truth tablewill have 64 rows.Task Three: Carry Lookahead Adder (5 pts)Suggested reading assignment: 5.10.41. (Pre) From the discussions of Task Two, it can be seen thatthe two-level expressions for Si and Ci+1, are verycumbersome. The problem is the increasingly complexexpressions for the Ci. that are obtained when the equationsare expanded out. Fortunately, the complexity of the carryoutputs may be reduced by using the ideas of carry-lookahead, which helps retain the simplicity of the recursivedesign equation of Task One while incorporating some ofthe two-level design speed of Task Two. We shall nowdefine a carry-generate signal Gi = Ai * Bi (i.e. generate acarry if both input bits are high) and carry-propagate signalPi = Ai + Bi (i.e. propagate a carry if either input bit is high).In terms of the carry generate and propagate definitions, thecarry-out condition may now be defined as Ci+1 = Gi + Pi *Ci. Here's your last prelab assignment: using the recursiveexpression described above and assuming that C0 = 0, derivenon-recursive expressions for the Ci+1 , for 0 ≤ i ≤ 2,involving only the Gi and Pi variables.2. Write the equations for the three-bit carry lookahead adderusing ABEL. Your instructor will give you a set of DIP-SWITCH/LED pin locations to assign to the Ai, Bi, Si andC3 variables by which you will be able to make a chip in thenext task. (Alternatively, an xsport command having theform 00 A2 A1 A0 B2 B1 B0 may be used, and the pinlocations would reflect this.)3. Employ the Functional Simulation software and check thesignal waveforms of your ABEL based design with theresults of Task Two. Do they agree?Task Four: Implementing Your Lookahead Adderin a ChipAfter completing the simulation of your fast adder circuit, youare now ready to construct a 3-bit adder in a chip, using yourcarry lookahead design as a basis, and program it into theXC95108 complex PLD chip residing on the XS95 board whichplugs in the XStend development environment. Make sure thatyour ABEL code included the pin locations of corresponding tothe dip switches that you will be employing as inputs.1. Go to the Program Manager and press the Implementbutton. This will bring up the XACT Design Managerwindow.2. Go to Design -> Implement in the Design Manager in thetop menu bar. You may be asked to enter a part number, inwhich case you must press Select and enter "XC9500" forFamily; "95108PC84" for Device, "PC84" for Package,and "20" for Speed. If the part is already specified thenyou will want to check Overwrite…3. Next press Run to begin the compilation. The Flow enginewindow next appears showing the steps between translation,fitting, timing and bitstream generation.4. When the compilation