Slide 1'&$%ECE/CE 3720: Embedded System DesignChris J. MyersLecture 8: Interrupts in the 68HC11Slide 2'&$%General Features of Interrupts• All interrupting systems must have the:1. Ability for hardware to request action from computer.2. Ability for computer to determine the source.3. Ability for computer to acknowledge the interrupt.• To arm (disarm) a device means to enable (shut off) thesource of interrupts.• To enable (disable) means to allow (postpone) interruptsat this time.1Slide 3'&$%Sequence of Events During Interrupt1. Hardwere needs service (busy-to-done) transition.2. Flag is set in one of the I/O status registers.(a) Interrupting event sets the flag (ex., STAF=1).(b) The device is armed (ex., STAI=1).(c) Microcomputer interrupts are enabled (ex., I=0).3. Thread switch.(a) Microcomputer finishes current instruction.(b) All registers are pushed onto the stack.(c) Vector address is obtained and put into the PC.(d) Microcomputer sets I=1.4. Execution of the ISR.5. Return control back to the thread that was running.Slide 4'&$%6811 Stack Before and After an Interrupt(See Figure 4.18)2Slide 5'&$%6811 Interrupts• 6811 has two external requestsIRQ and XIRQ.• Other interrupt sources include:– A STRA interrupt– Three input capture interrupts– Five output capture interrupts– Three timer interrupts (timer overflow, RTI, pulseaccumulator)– Two serial port interrupts (SCI and SPI)Slide 6'&$%6811 Interrupts• Interrupts have a fixed priority, but can elevate one tohighest priority using hardware priority interrupt(HPRIO) register.• XIRQ is highest-priority device and has separate vectorand enable bit (X).• Once X bit is cleared, software cannot disable it.• XIRQ handler sets X and I, and restores with rti.3Slide 7'&$%6811 Interrupt Vectors and PriorityVector Interrupt Source Enable Arm$FFFE Power on reset Always Always highest$FFFE Hardware reset Always Always$FFFC COP clk monitor fail Always OPTION.CME=1$FFFA COP failure Always CONFIG.NOCOP=0$FFF4 Nonmaskable XIRQ X=0 External hardware$FFF2 External IRQ I=0 External hardware$FFF2 Parallel I/O, STAF I=0 PIOC.STAI=1$FFF0 Real time int., RTIF I=0 TMSK2.RTII=1$FFEE Inp capture 1, IC1F I=0 TMSK1.IC1I=1$FFEC Inp capture 2, IC2F I=0 TMSK1.IC2I=1$FFEA Inp capture 3, IC3F I=0 TMSK1.IC3I=1$FFE8 Outp capture 1, OC1F I=0 TMSK1.OC1I=1$FFE6 Outp capture 2, OC2F I=0 TMSK1.OC2I=1$FFE4 Outp capture 3, OC3F I=0 TMSK1.OC3I=1Slide 8'&$%6811 Interrupt Vectors and Priority (cont)Vector Interrupt Source Enable Arm$FFE2 Outp capture 4, OC4F I=0 TMSK1.OC4I=1$FFE0 Outp capture 5, OC5F I=0 TMSK1.OC5I=1$FFDE Timer overflow, TOF I=0 TMSK2.TOI=1$FFDC Pulse accum overflow I=0 TMSK2.PAOVI=1$FFDA Pulse accum inp edge I=0 TMSK2.PAII=1$FFD8 SPI complete,SPIF I=0 SPCR.SPIE=1$FFD6 Rx data reg full, RDRF I=0 SCCR2.RIE=1$FFD6 Rx overrun, OVRN I=0 SCCR2.RIE=1$FFD6 Tx data reg full, TDRE I=0 SCCR2.TIE=1$FFD6 Tx complete, TC I=0 SCCR2.TCIE=1$FFD6 Idle line detect, IDLE I=0 SCCR2.ILIE=1$FFF8 Illegal opcode trap Always Always$FFF6 Software interrupt SWI Always Always lowest4Slide 9'&$%Setting Interrupt Vectorsorg $FFF0fdb RTIHAN Ptr to real time interrupt handlerorg $FFF2fdb IRQHAN Ptr to external IRQ and STRA handlerorg $FFF4fdb XIRQHAN Ptr to external XIRQ handlerorg $FFFEfdb RESETHAN Ptr to reset handlerSlide 10'&$%6811 Pseudo-Vectors6811 Vector Vector Name Address$FFD6 SCI $00C4-$00C6$FFD8 SPI $00C7-$00C9$FFDA Pulse accum inp edge $00CA-$00CC$FFDC Pulse accum overflow $00CD-$00CF$FFDE Timer overflow, TOF $00D0-$00D2$FFE0 Outp capture 5, OC5F $00D3-$00D5$FFE2 Outp capture 4, OC4F $00D6-$00D8$FFE4 Outp capture 3, OC3F $00D9-$00DB$FFE6 Outp capture 2, OC2F $00DC-$00DE$FFE8 Outp capture 1, OC1F $00DF-$00E15Slide 11'&$%6811 Pseudo-Vectors (cont)6811 Vector Vector Name Address$FFEA Inp capture 3, IC3F $00E2-$00E4$FFEC Inp capture 2, IC2F $00E5-$00E7$FFEE Inp capture 1, IC1F $00E8-$00EA$FFF0 Real time int., RTIF $00EB-$00ED$FFF2 External IRQ, STAF $00EE-$00F0$FFF4 Nonmaskable XIRQ $00F1-$00F3$FFF6 Software interrupt SWI $00F4-$00F6$FFF8 Illegal opcode trap $00F7-$00F9$FFFA COP failure $00FA-$00FC$FFFC COP clk monitor fail $00FD-$00FFSlide 12'&$%Setting Interrupt Pseudo-Vectorsldaa #$7E Opcode for JMPstaa $00EBldx #RTIHAN Ptr to real time interrupt handlerstx $00EC JMP RTIHANldaa #$7E Opcode for JMPstaa $00EEldx #IRQHAN Ptr to external IRQ and STRA handlerstx $00EF JMP IRQHANldaa #$7E Opcode for JMPstaa $00F1ldx #XIRQHAN Ptr to external IRQ and STRA handlerstx $00F2 JMP XIRQHAN6Slide 13'&$%External Interrupt Design Approach• First, identify status signal that indicates thebusy-to-done state transition.• Next, connect the I/O status signal to a microcomputerinput that can generate interrupts.(See Figure 4.21)Slide 14'&$%Interrupting Software1. Ritual - executed once, disable interrupts during,initialize globals, set port dir, set port interrupt ctrl reg,clear interrupt flag, arm device, and enable interrupts.2. Main program - initialize SP, execute ritual, interactswith ISRs via global data (ex. FIFO queue).3. ISR(s) - determine interrupt source, implement priority,acknowledge (clear the flag) or disarm, exchange infow/main program via globals, execute rti to exit.4. Interrupt vectors - in general purpose processors vectorsin RAM, in embedded systems usually in ROM.7Slide 15'&$%Polled Versus Vectored Interrupts• Vectored interrupts - each interrupt source has a uniqueinterrupt vector address.• Polled interrupts - multiple interrupt sources share thesame interrupt vector address.– Minimal polling - check flag bit that caused interrupt.– Polling for 0s and 1s - verify entire status register.Slide 16'&$%External I/O Device(s) Connected to theMicrocomputer(See Figures 4.22 and 4.23)8Slide 17'&$%Example of a Vectored InterruptTimeHan ldaa #$80 ;TOF is bit 7staa TFLG2 ;clear TOF;*Timer interrupt calculations*rtiExtHan ldaa PIOCldaa PORTCL ;clear STAF;*External interrupt calculations*rtiorg $FFDE ;timer overflowfdb TimeHanorg $FFF2 ;IRQ externalfdb ExtHanSlide 18'&$%Example of a Polled InterruptExtHan ldaa PIOC ;which onebita #$80 ;STAF?bne STAFHanldaa OtherStatus1bita #$80 ;External?bne OtherHanswi ;errorSTAFHan ldaa PORTCL ;clear STAF;*STAF interrupt calculations*rtiOtherHan ldaa OtherData;*Other interrupt calculations*rtiorg $FFF2 ;IRQ externalfdb ExtHan9Slide 19'&$%Keyboard Interface Using Interrupts(See Figures 4.24, 4.25, and 4.26)Slide 20'&$%Interrupting Keyboard Software in C// PC6-PC0 inputs = key DATA, STRA=STROBE interruptvoid