Slide 1'&$%ECE/CS 3720: Embedded System Design(ECE 6960/2 and CS 6968)Chris J. MyersLecture 23: Memory InterfacingSlide 2'&$%Introduction• Most embedded systems use only the memory built-in tothe microcontroller.• Memory interfacing and bus timing is important tounderstanding internal microcontroller architecture.• Sometimes internal memory is insufficient, and externalmemory must be used.• Sometime external devices must be interfaced usingmemory-mapped I/O.1Slide 3'&$%Memory-Mapped I/OSlide 4'&$%Isolated I/O2Slide 5'&$%6811 Expanded ModeSelect R/W Function0 0 Off0 1Off1 0Write1 1ReadSlide 6'&$%Multiplexed Address and Data Lines3Slide 7'&$%Full-Address Decoding• Slave selected only when slave’s address is on the bus.• Design using the following steps:1. Write specified address using 0,1,X:0100,00XX,XXXX,XXXX for 1K RAM at $4000-$43FF2. Write equation using all 0s and 1s:select =A15 · A14 · A13 · A12 · A11 · A103. Build circuit using gates.Slide 8'&$%Address Decoder for 1K RAM at $4000-$43FF4Slide 9'&$%An Address Decoder for I/O Device at $5500Slide 10'&$%Minimal-Cost Address Decoding• Use don’t cares for unspecified addresses to simplify.• Example:4K RAM $0000 to $0FFF 0000,XXXX,XXXX,XXXXInput $5000 0101,0000,0000,0000Output $5001 0101,0000,0000,000116K ROM $C000 to $FFFF 11XX,XXXX,XXXX,XXXX5Slide 11'&$%An Address DecoderSlide 12'&$%Karnaugh Maps6Slide 13'&$%Special Cases• Size of the memory is not a power of 2.20K RAM with address range $0000 to $4FFF00XX,XXXX,XXXX,XXXX Range $0000 to $3FFF0100,XXXX,XXXX,XXXX Range $4000 to $4FFF• Start address divided by memory size not an integer.32K RAM with address range $2000 to $9FFF001X,XXXX,XXXX,XXXX Range $2000 to $3FFF01XX,XXXX,XXXX,XXXX Range $4000 to $7FFF100X,XXXX,XXXX,XXXX Range $8000 to $9FFFSlide 14'&$%Programmable Address DecoderIn Mn An Vn Out0 X X X 01 0 X X 11 1 0 011 1 1 0 01 1 0 1 01 1 1 107Slide 15'&$%Timing Intervals(↑ Y, ↓ Y ) = (↓ A, ↑ A) + 10(↑ Y, ↓ Y ) = (↓ A, ↑ A) + [5, 15](↑ Y, ↓ Y ) = (↓ A + [8, 15], ↑ A + [5, 12])Slide 16'&$%Available and Required Time IntervalsDA = (↓ G∗+ [10, 20], ↑ G∗+ [0, 15])DA = (↓ G∗+ 20, ↑ G∗) worst-caseDR = (↑ Clk − 30, ↑ Clk + 5)8Slide 17'&$%Timing DiagramsSlide 18'&$%Example Timing Diagrams9Slide 19'&$%Read CycleSlide 20'&$%Write Cycle10Slide 21'&$%Synchronous Bus TimingSlide 22'&$%Partially Asynchronous Bus Timing(6809/680x0/x86)11Slide 23'&$%Fully Asynchronous Read CycleSlide 24'&$%Fully Asynchronous Write Cycle12Slide 25'&$%Four Types of Control SignalsSlide 26'&$%6811 Expanded Mode• In single chip mode, Port B, PortC, STRA, and STRBare used for I/O.• In expanded mode:– Port B is the high address bits– Port C is the low address and data bits– STRA is the address strobe AS, and– STRB is the R/W line.13Slide 27'&$%6811 Expanded Mode Bus TimingSlide 28'&$%6811 Four Types of Control Signals14Slide 29'&$%General Approach to Memory InterfacingSlide 30'&$%Read Timing for 32K PROM15Slide 31'&$%6811/32K PROM InterfaceSlide 32'&$%6811/32K PROM Interface Timing16Slide 33'&$%8K RAM Read TimingSlide 34'&$%8K RAM Write Timing17Slide 35'&$%8K RAM Write TimingSlide 36'&$%Unsynchronized Signals18Slide 37'&$%6811/8K RAM InterfaceSlide 38'&$%6811/8K RAM Interface Read Timing19Slide 39'&$%6811/8K RAM Interface Write TimingSlide 40'&$%Dynamic RAM (DRAM)DRAMs SRAMsHigh density Low densityOne xtor, one cap./bit 3-4 xtors/bitSlower FasterHigh fixed cost (refresh) Low fixed cost (address decoder)Low incremental cost Higher incremental costAddress multiplexing Direct
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