Lecture 6 EE 486M.J. Flynn 1Computer Architecture & Arithmetic Group 1 Stanford UniversityEE 486 lecture 6: Integer AdditionM. J. FlynnComputer Architecture & Arithmetic Group 2 Stanford UniversityComputer Architecture & Arithmetic Group 3 Stanford UniversityAddition• The add function is fundamental todetermining processor cycle time and henceoverall performance.• Add algorithms have been widely studied,so that there are many apparently differentalgorithms that actually differ only in someminute detail.Computer Architecture & Arithmetic Group 4 Stanford UniversityAdd algorithms• ripple add: the baseline,• carry skip adders• carry selection adds• carry propagating adds• Ling adds• carry saving add• hybrid addComputer Architecture & Arithmetic Group 5 Stanford UniversityRipple adders• the baseline: 2n gate delays• Manchester carry chain• carry completionComputer Architecture & Arithmetic Group 6 Stanford UniversityBit logic• (in the following V means exclusive OR)• Sum: si = ai V bi V ci• Carry out: ci+1 =aibi + bici + aici• Propagate: pi = ai + bi• Generate: gi = aibi• Carry out is also: ci+1 = gi + piciLecture 6 EE 486M.J. Flynn 2Computer Architecture & Arithmetic Group 7 Stanford UniversityManchester adders• Use a single pass transistor to implementthe pi and another to implement gi• Fast serial carry chain up to a circuit limit,less than 8, usually much less. As chain getlonger the capacity seen by the driverincreases quadratically.Computer Architecture & Arithmetic Group 8 Stanford UniversitySimplified Manchester carry bitChain for CoutComputer Architecture & Arithmetic Group 9 Stanford UniversityCarry completion• Asynchronous adder: E(l) = log2 n• Create two carry out signals, ci =1and ci =0• then ci+1 = gi + pici and if di+1 is thecomplement of ci+1• then we must have (ci+1 + di+1) = 1 for eachof the i bits to detect completion (ANDed)Computer Architecture & Arithmetic Group 10 Stanford UniversityCarry skip adders• single level, multiple levels• fixed block size, variable block size• the multi level, fixed block is a type of carrylook ahead• Babbage’s “carriage anticipation”is a carryskip adderComputer Architecture & Arithmetic Group 11 Stanford UniversityCarry Skip logic•Computer Architecture & Arithmetic Group 12 Stanford UniversityCarry skip• Bypass logic for carries based on bitpropagate terms• So Pi = (p3p2p1) ci has group Pi up to a fanin limit, r (r=4, above)• In 2 gate delays the carry span a group.• Can create a group of groups for faster add.Lecture 6 EE 486M.J. Flynn 3Computer Architecture & Arithmetic Group 13 Stanford UniversityCarry skip• Spans r-1 bits with r limited AND; C2=G1+(p3p2p1) C1 needs 2 gate delays• If the carry is rippled in the first and lastblock the (single level) skip delay is theripple delay + the skip delay• t = 4(r-1) +2([n/(r-1)] –2)Computer Architecture & Arithmetic Group 14 Stanford UniversityCarry select• conditional sum• carry select (Bedrij)• the carry select type adder is widely used asa component in a hybrid adder.Computer Architecture & Arithmetic Group 15 Stanford UniversityConditional sum• Partition the n bit operands into n/r bit digits• For each r-limited digit, form sE and sN , cEand cN based on cin =1 for sE , cE and cin =0for sN , cN• Partition into digit pairs and determine thesE sE , cE and the sN sN , cN result.• Continue now for 4 digit groups, etcComputer Architecture & Arithmetic Group 16 Stanford UniversityConditional sum• Logic within a 4 bit digit– SN0=A0 V B0 ; SE0 = ~ SN0– SN1= A1V B1VG0 ; SE1 = A1V B1VP0– SN2= A2V B2V(G1+P1G0);SE2=A2VB2V(G1+P1P0)– SN3= A3V B3V(G2+ +P2G1 +P2P1G0);– SE3= A3VB3V(G2+ +P2G1 +P2P1P0);– CN4 = G3+ P3G2 +P3P2G1+P3P2P1G0– CE4 = G3+ P3G2 +P3P2G1+P3P2P1P0Computer Architecture & Arithmetic Group 17 Stanford UniversityConditional sum• For digit pairs the carry outs are– CE2 = G1+P1P0– CN2 = G1+P1G0• The sum pairs, E and N are selected so thatthe lsd’s are unaffected and the the msd’sare unaffected if their carry ins differ, but ifboth carry in = 0 replace SE with SN and ifboth carry in = 1 replace SN with SEComputer Architecture & Arithmetic Group 18 Stanford UniversityCarry select• Rather than selecting by pairs we can selectup to a fan in limit (r-1)• C4=CN4 +CE4C0• C8=CN8 +CE8C4• C12=CN12 +CE12C8 = CN12 +CE12CN8 +CE12CE8 CN4 + CE12CE8 CE4C0Lecture 6 EE 486M.J. Flynn 4Computer Architecture & Arithmetic Group 19 Stanford UniversityComputer Architecture & Arithmetic Group 20 Stanford UniversityComputer Architecture & Arithmetic Group 21 Stanford UniversityCarry select delay• Delay consists of digit addition, carrypropagation and final sum selection• Selection is a MUX:S4= SE4C0+SN4C0• Delay is = k + 2[log r-1([n/r]-1)]Computer Architecture & Arithmetic Group 22 Stanford UniversityCarry propagating adders• The most widely studied class of adder:– carry look ahead– canonic– prefix addersComputer Architecture & Arithmetic Group 23 Stanford UniversityCLA: carry look ahead adders• Form p, g terms for each bit, i• Then C1 = G0+ P0C0; C2 = G1+ P1C1• C3 = G2+ P2G1 +P2P1G0+P2P1P0C0• C4 = G3+ P3G2 +P3P2G1+P3P2P1G0+P3P2P1P0C0• Group generate:G3+P3G2+P3P2G1+P3P2P1G0• Group propagate: P3P2P1P0Computer Architecture & Arithmetic Group 24 Stanford UniversityGroup generate(G’) and Grouppropagate(P’)• C4 = G’0+ P’0C0• C8 = G’1+ P’1G’0 +P’1P’0C0• C12 = G’2+ P’2G’1+P’2P’1G’0+P’2P’1P’0C0• G’’0 =