EE 486 Winter 02-03M. J. Flynn 1Computer Architecture & Arithmetic Group 1 Stanford UniversityEE 486 : lecture 3, more on IEEE and IEEE vs. Cray arithmeticM. J. FlynnComputer Architecture & Arithmetic Group 2 Stanford UniversityLecture 2, slide 13 update.IEEE format, the basics• Single: (32b) s+e+m bit layout is 1+8+23 Double: (64b) 1+ 11 +52; also quad• Extended: (44b) 1+11+32 and (80b) 1+15+64 for register only operations; no hidden one used in an extended format. • β = 2 with S + M representation• Hidden 1 to the left of radix point (1).xxx• Exponent bias (2e/2) -1 not 2e/2Computer Architecture & Arithmetic Group 3 Stanford UniversityGuard bits and rounding• The rounding of the result adds A after post normalization1.G SL.First must combine R and S and then add A to the G bitA is derived from L, G and SComputer Architecture & Arithmetic Group 4 Stanford UniversityAction table, A, for RN1Round to nearest11X1Tie case with odd L, round to even0110Tie case with even L, no rounding0100Inexact result, but significand rounded10X0Exact result, no round00XAActionSGLComputer Architecture & Arithmetic Group 5 Stanford UniversityGetting the guard bits and rounding• Before post normalization result should be computed toX G’ R’S’L’L’ is the lsb, N’ is the lsb plus 1; G’ is first guard digit, round bit R’ is the second guard bit and S’ in the sticky bit (the OR of all lower order bits.)X. N’Computer Architecture & Arithmetic Group 6 Stanford UniversityGuard bits and rounding• Before post normalization result can be– XX.XX… on +/* 4.0> r >or = 1.0; this requires 0 or 1 right shift.– On divide since rmin= 1.0/(2-ulp) then 2.0 > r > ½; so one left shift may be required– On subtraction, can have massive cancellation so m-1 left shifts can be required.EE 486 Winter 02-03M. J. Flynn 2Computer Architecture & Arithmetic Group 7 Stanford UniversityFinding LGS from L’G’R’S’• After post normalization:– Case 1 no shift G=G’ ; S= R’+S’– Case 2 one right shift L=N’; G=L’; S=S’+G’+R’– Case 3 one left shift L=G’; G=R’; S=S’– Case 4 >1 left shift. Can only occur on (a-b) where a,b exponents differ by 0 or 1. So L’G’are left shifted into result and R=0 and S=0 (as R’ and S’ must also be 0)Computer Architecture & Arithmetic Group 8 Stanford UniversityA, the rounding action• A is added to the G bit to produce rounded result.• Commonly A selects from MUX either result or result+1.• Must define A for each rounding mode; preferably before post normalization.Computer Architecture & Arithmetic Group 9 Stanford UniversityIEEE reserved operands and denormal numbersNAN not a numberNot 0255X- infinity02551+ infinity02550+/- a denormalized numberNot 000/1- zero001+ zero000Meaning SignificandBiased expS, signComputer Architecture & Arithmetic Group 10 Stanford UniversityDenormal numbers• Min is (1).0 * 2-126• Denormal has no hidden 1, so (min – ulp) is 0.11111…1 * 2-126; this is the same as 1.111…* 2-127This is the largest denormal.• Min denormal is 0.0000000…….01*2-126.• Denormals may have minimum significance if used by subsequent up-scaling operations.Computer Architecture & Arithmetic Group 11 Stanford UniversityIEEE exceptions• Five conditions– Invalid ops and NANs– Overflow– Division by 0– Underflow– Inexact result• Exceptions are handled by either trap or by disabled trap and continuing operation.Computer Architecture & Arithmetic Group 12 Stanford UniversityTraps disabled• Invalid ops: e.g. (sqrt of –5) produces NAN, then the NAN propagates as a valid result, e.g. 5 x NAN =NAN• Overflows: set to +/- infinity and continue• Divide by 0: set to +/- infinity• Underflow: set to denormal and then to 0• Inexact: continue (used only for integer arithmetic)EE 486 Winter 02-03M. J. Flynn 3Computer Architecture & Arithmetic Group 13 Stanford UniversityTraps enabled• On overflow/ underflow: adjust char (remove bias on overflow, add k on under) to bring exp into useful range• On invalid: use the NAN format to provide a useful pointer (user discretion)• Inexact result: if G and S =0 then exact; otherwise inexact, trap to continue to protect integer computation.Computer Architecture & Arithmetic Group 14 Stanford UniversityCan FPN satisfy the laws of algebra?• Idempotency: 1x X=X or X +/- 0 = X for all X..this should be OK; but converse fails so that if (a x X) = a, X need not be 1 and if (a +/- X) = a, then X need not =0.• Commutation: a + b = b + a and a x b=b x a should be OK, but some designs fail• Associative: a + (b+c) = (a+b) +c fails• Distributive: (a+b) x c = a x c + b x c failsComputer Architecture & Arithmetic Group 15 Stanford UniversityResult sequencing• In FP, ops should appear to be computed as a serial sequence of sub-ops– Operand capture and validation– Compare and exponent difference– Significand alignment (pre shift)– Operation – Recomplement– LOD and post shift to renormalize – Round and final renormalizeComputer Architecture & Arithmetic Group 16 Stanford UniversityCray (ca.’76): quick and dirty FPN• Layout is s + e +f = 1 +15 +48 =64b• β = 2, bias is 215/2 =214= 16,384• Fraction is 0.1xx.., no hidden 1• Max exp is = 213-1= 8,191 (not 214-1)• Overflow, o, occurs when leading 2 bits of char =11 (exp is 8,192), set flag• Underflow when leading 2 bits of char = 00 (exp is –8,191); set r to 0, no trap.Computer Architecture & Arithmetic Group 17 Stanford UniversityMore Cray• But determine o and underflow before (!) post normalization• No validity test on input operands (except 0 test)• Only partial build out of multiplier tree• So (min + s) – min = s where s can be 2-48less that min. Max * 1.0 gives o. Early models didn’t give X * Y = Y * X.Computer Architecture & Arithmetic Group 18 Stanford UniversityYet more Cray• Can produce small=min*2-48as output, but recognized as “0” on input, so small*1.0 = 0• Can ignore o trap and continue since o char is 11XXXX. But o * 0 = 0.• Integer ops available; integers have all zero char for both char.EE 486 Winter 02-03M. J. Flynn 4Computer Architecture & Arithmetic Group 19 Stanford UniversityFPNs• In many applications (eg DSP) you don’t need a robust FPN, compromises in FPN can give more effective designs.• Some