Lecture 7 EE 486M.J. Flynn 1Computer Architecture & Arithmetic Group 1 Stanford UniversityEE 486 lecture 7: Integer MultiplicationM. J. Flynnslides prepared by Albert Liddicoat and Hossam FahmyComputer Architecture & Arithmetic Group 2 Stanford UniversityMultiplication Add-and-Shift AlgorithmMultiplicandMultiplierPartial ProductsResult1 1 01 0 11 1 00 0 01 1 01 1 1 1 0“X”“Y”“PP”“S”6530x xALUXYP0ShiftShiftComputer Architecture & Arithmetic Group 3 Stanford UniversityParallel Multiplication1 Simultaneous generation of partial products2 Parallel reduction of partial products3 Carry Propagate Addition (CPA)Parallel generation of partial productsX0X1Y2Y1Y0X0Y0X1Y0X2Y0X0Y1X1Y1X2Y1X0Y2X1Y2X2Y2R0R1R2R3R4R5xX2...X0X1Y2Y1Y0xX2............Using AND gate as 1x1-bit multiplier DOT representationComputer Architecture & Arithmetic Group 4 Stanford UniversityGeneration of PP’s Using ROMsAddressData256x8-bit ROMXYR4b x 4b Multiply UsingX3X2X1X0X7X6X5X4Y3Y2Y1Y0Y7Y6Y5Y4X3X2X1X0* Y3Y2Y1Y0* Y3Y2Y1Y0X7X6X5X4* Y7Y6Y5Y4* Y7Y6Y5Y4X3X2X1X0X7X6X5X4x8b x 8b Multiply Using256x8-bit ROMsComputer Architecture & Arithmetic Group 5 Stanford UniversityGeneration of PP’s Using ROMsabcdacbd8 x 8 bit Multiply using256x8b ROMs4x4 bit8x8 bit16x16 bit4, 8, and 16 bit Multiply using 256x8bit ROMsnh CSA Delay48163264137153101468Computer Architecture & Arithmetic Group 6 Stanford UniversityBooth’s AlgorithmObservation: We can replace a string of 1’s in the multiplier by +1 and -1.Example:. . . 0 1 1 1 1 1 0 . . .+1- 1. . . 1 0 0 0 0 0 0 . . .- 1. . . 1 0 0 0 0-1 0 . . .. . . 0 1 1 1 1 1 0 . . .XXXXXX*(0 1 1 1 1 1)0111101YX*(1 0 0 0 0-1)-X000000001-1YXLecture 7 EE 486M.J. Flynn 2Computer Architecture & Arithmetic Group 7 Stanford UniversityBooth’s Algorithm+ Reduces the number of partial products which in turn reduces thehardware and delay required to sum the partial products.- Adds Delay into the formation of the Partial Products.• Works well for serial multiplication that can tolerate variable latency operations by reducing the number of serial additions required for the multiplication.• The number of serial additions depends on the data (multiplicand).• Worst case 8-bit multiplicand requires 8 additions01010101 <=> 1 -1 1 -1 1 -1 1 -1• Parallel systems generally are designed for worst case hardware and latency requirements. Standard booth 2 does not significantly reduce the worst case number of partial products.Computer Architecture & Arithmetic Group 8 Stanford UniversityModified Booth 2 • Booth 2 modified to produce at most n/2+1 partial products. Algorithm: (for unsigned numbers)1) Pad the LSB with one zero.2) Pad the MSB with 2 zeros if n is even and 1 zero if n is odd. 3) Divide the multiplier into overlapping groups of 3-bits.4) Determine partial product scale factor from modified booth 2 encoding table.5) Compute the Multiplicand Multiples6) Sum Partial ProductsComputer Architecture & Arithmetic Group 9 Stanford UniversityModified Booth 20 0 Y7Y6Y5 Y4 Y3Y2Y1Y00 Example: (n=8-bits unsigned)YiYi+1Yi-1ScaleFactor00011110 0011001101010101+0+X+X+2X-2X-X-X-03) Form 3-bit overlapping groupsfor n=8 we have 5 groups1) Pad LSB with 1 zero2) n is even so Pad MSB with 2 zeros4) Determine action fromtable for each 3-bit groupComputer Architecture & Arithmetic Group 10 Stanford UniversityModified Booth 25) Compute Multiplicand Scale Factor (~4 gate delays)YjXiPPijXiXi-10Yj+1YjYj-1PPijDirect Multiplier Modified Booth 2 Multiplier Mux Control LogicScaleFactorAction+0 Mux 0+X+2X-2X-XMux XiMux Xi-1Mux Xi-1’Mux Xi’Computer Architecture & Arithmetic Group 11 Stanford UniversityModified Booth 26) Sum Partial Products• Sign extend partial products to the full width of the final result• Logic may replace the A9, B9, C9, D9, and E9sign extention bits.• Yi+1bit determines if the multiple needs to be complemented A9. . .A9A9A8A7A6A5A4A3A2A1A0B9. . . B8B7B6B5B4B3B2B1B0 Y1C9. . . C6C5C4C3C2C1C0Y3D9. . .D4D3D2D1D0Y5E9. . . E2E1E0Y7S15. . . S10S9S8S7S6S5S4S3S2S1S0(Y1Y00 ) (Y3Y2Y1) (Y5Y4Y3) (Y7Y6Y5) ( 0 0 Y7) Partial ProductsMultiplicandYi+1YiYI-1Computer Architecture & Arithmetic Group 12 Stanford UniversityModified Booth 2Algorithm Extension: (for signed multiplier)1) Pad the LSB with one zero.2) If n is even don’t pad the MSB ( n/2PP’s) and if n is odd sign extend the MSB by 1 bit ( n+1/2PP’s). 3) Divide the multiplier into overlapping groups of 3-bits.4) Determine partial product factor from table. 5) Compute the Multiplicand Multiples6) Sum Partial Productsn Even:Xn-1 Xn-2Xn-20 x x 1 x x n Odd:Ø Xn-1 Xn-20 0 x 1 1 x Positive:Negative:Lecture 7 EE 486M.J. Flynn 3Computer Architecture & Arithmetic Group 13 Stanford UniversityModified Booth 2Algorithm Extension: (for signed multiplicand)Nothing the algorithm works fine !• The multiplicand may be represented in 2’s complement code.• The scale factors (0, +X, +2X, -X, and -2X) are handled correctly.• Shift left for 2 times weighting.•2’s complement the multiplicand for subtraction.Computer Architecture & Arithmetic Group 14 Stanford UniversityBooth 3 • Reduces the partial products to ~n/3• Form overlapping groups of 4 bits.0 Y7Y6Y5 Y4 Y3Y2Y1Y00 • Booth 3 EncodingYiYi+1Yi-1ScaleFactor00011110 0011001101010101-4X-3X-2X-2X-X-X-0Yi+211111111YiYi+1Yi-1ScaleFactor00011110 0011001101010101+0+X+X+2X+2X+3XYi+200000000+3X+4X-3XNote: 3x is a hardmultiple that must be precomputedComputer Architecture & Arithmetic Group 15 Stanford UniversityPartially Redundant Booth 3Computer Architecture & Arithmetic Group 16 Stanford UniversityPartially Redundant Booth