4_124_134_14Chapter 4The ProcessorChapter 4 — The Processor — 2Stalls and Performance Stalls reduce performance But are required to get correct results Compiler can arrange code to avoid hazards and stalls Requires knowledge of the pipeline structureThe BIG PictureChapter 4 — The Processor — 3Control Hazards Branch determines flow of control Fetching next instruction depends on branch outcome Pipeline can’t always fetch correct instruction Still working on ID stage of branch In MIPS pipeline Need to compare registers and compute target early in the pipeline Add hardware to do it in ID stageDealing With Branch Hazards Hardware solutions stall until you know which direction branch goes guess which direction, start executing chosen path (but be prepared to undo any mistakes!) static branch prediction: base guess on instruction type  dynamic branch prediction: base guess on execution history reduce the branch delayChapter 4 — The Processor — 5Stall on Branch Wait until branch outcome determined before fetching next instructionChapter 4 — The Processor — 6Branch Prediction Longer pipelines can’t readily determine branch outcome early Stall penalty becomes unacceptable Predict outcome of branch Only stall if prediction is wrong In MIPS pipeline Can predict branches not taken Fetch instruction after branch, with no delayChapter 4 — The Processor — 7MIPS with Predict Not TakenPrediction correctPrediction incorrectChapter 4 — The Processor — 8More-Realistic Branch Prediction Static branch prediction Based on typical branch behavior Example: loop and if-statement branches Predict backward branches taken Predict forward branches not taken Dynamic branch prediction Hardware measures actual branch behavior e.g., record recent history of each branch Assume future behavior will continue the trend When wrong, stall while re-fetching, and update historyChapter 4 — The Processor — 9Branch Hazards If branch outcome determined in MEM§4.8 Control HazardsPCFlush theseinstructions(Set controlvalues to 0)Chapter 4 — The Processor — 10Reducing Branch Delay Move hardware to determine outcome to ID stage Target address adder Register comparator Example: branch taken36: sub $10, $4, $840: beq $1, $3, 744: and $12, $2, $548: or $13, $2, $652: add $14, $4, $256: slt $15, $6, $7...72: lw $4, 50($7)Chapter 4 — The Processor — 11Example: Branch TakenChapter 4 — The Processor — 12Example: Branch TakenChapter 4The ProcessorChapter 4 — The Processor — 2Data Hazards for Branches If a comparison register is a destination of 2ndor 3rdpreceding ALU instruction…IF ID EX MEM WBIF ID EX MEM WBIF ID EX MEM WBIF ID EX MEM WBadd $4, $5, $6add $1, $2, $3beq $1, $4, target Can resolve using forwardingChapter 4 — The Processor — 3Data Hazards for Branches If a comparison register is a destination of preceding ALU instruction or 2ndpreceding load instruction Need 1 stall cyclebeq stalledIF ID EX MEM WBIF ID EX MEM WBIF IDID EX MEM WBadd $4, $5, $6lw $1, addrbeq $1, $4, targetChapter 4 — The Processor — 4Data Hazards for Branches If a comparison register is a destination of immediately preceding load instruction Need 2 stall cyclesbeq stalledIF ID EX MEM WBIF IDIDID EX MEM WBbeq stalledlw $1, addrbeq $1, $0, targetChapter 4 — The Processor — 5Dynamic Branch Prediction In deeper and superscalar pipelines, branch penalty is more significant Use dynamic prediction Branch prediction buffer (aka branch history table) Indexed by recent branch instruction addresses Stores outcome (taken/not taken) To execute a branch Check table, expect the same outcome Start fetching from fall-through or target If wrong, flush pipeline and flip predictionChapter 4 — The Processor — 61-Bit Predictor: Shortcoming Inner loop branches mispredicted twice!outer: ……inner: ……beq …, …, inner…beq …, …, outer Mispredict as taken on last iteration of inner loop Then mispredict as not taken on first iteration of inner loop next time aroundChapter 4 — The Processor — 72-Bit Predictor Only change prediction on two successive mispredictionsChapter 4 — The Processor — 8Calculating the Branch Target Even with predictor, still need to calculate the target address 1-cycle penalty for a taken branch Branch target buffer Cache of target addresses Indexed by PC when instruction fetched If hit and instruction is branch predicted taken, can fetch target immediatelyChapter 4The ProcessorChapter 4 — The Processor — 2Exceptions and Interrupts “Unexpected” events requiring changein flow of control Different ISAs use the terms differently Exception Arises within the CPU e.g., undefined opcode, overflow, syscall, … Interrupt From an external I/O controller Dealing with them without sacrificing performance is hard§4.9 ExceptionsChapter 4 — The Processor — 3Handling Exceptions In MIPS, exceptions managed by a System Control Coprocessor (CP0) Save PC of offending (or interrupted) instruction In MIPS: Exception Program Counter (EPC) Save indication of the problem In MIPS: Cause register We’ll assume 1-bit 0 for undefined opcode, 1 for overflow Jump to handler at 8000 00180Chapter 4 — The Processor — 4An Alternate Mechanism Vectored Interrupts Handler address determined by the cause Example: Undefined opcode: C000 0000 Overflow: C000 0020 …: C000 0040 Instructions either Deal with the interrupt, or Jump to real handlerChapter 4 — The Processor — 5Handler Actions Read cause, and transfer to relevant handler Determine action required If restartable Take corrective action use EPC to return to program Otherwise Terminate program Report error using EPC, cause, …Chapter 4 — The Processor — 6Exceptions in a Pipeline Another form of control hazard Consider overflow on add in EX stageadd $1, $2, $1 Prevent $1 from being clobbered Complete previous instructions Flush add and subsequent instructions Set Cause and EPC register values Transfer control to handler Similar to mispredicted branch Use much of the same hardwareChapter 4 — The Processor — 7Pipeline with ExceptionsChapter 4 — The Processor — 8Exception Properties