4_14_24_3Chapter 4The ProcessorChapter 4 — The Processor — 2Introduction CPU performance factors Instruction count CPI and Cycle time We will examine two MIPS implementations A single-cycle implementation A pipelined version Simple subset, shows most aspects Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j§4.1 IntroductionChapter 4 — The Processor — 3Instruction Execution PC  instruction memory, fetch instruction Register numbers  register file, read registers Depending on instruction class Use ALU to calculate Arithmetic result Memory address for load/store Branch target address Access data memory for load/store PC  target address or PC + 4Chapter 4 — The Processor — 4CPU OverviewChapter 4 — The Processor — 5Multiplexers Can’t just join wires together Use multiplexersChapter 4 — The Processor — 6ControlChapter 4 — The Processor — 7Logic Design Basics§4.2 Logic Design Conventions Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational element Operate on data Output is a function of input State (sequential) elements Store informationChapter 4 — The Processor — 8Combinational Elements AND-gate Y = A & BABYI0I1YMuxS Multiplexer Y = S ? I1 : I0ABY+ABYALUF Adder Y = A + B Arithmetic/Logic Unit Y = F(A, B)Chapter 4 — The Processor — 9Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1DClkQClkDQChapter 4 — The Processor — 10Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required laterDClkQWriteWriteDQClkChapter 4 — The Processor — 11Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay determines clock periodChapter 4The ProcessorChapter 4 — The Processor — 2Building a Datapath Datapath Elements that process data and addressesin the CPU Registers, ALUs, mux’s, memories,  We will build a MIPS datapath incrementally Refining the overview design§4. Building a DatapathChapter 4 — The Processor — 3Instruction etch2-bit registerIncrement by 4 for next instructionChapter 4 — The Processor — 4ormat Instructions Read two register operands Perform arithmetic/logical operation Write register resultChapter 4 — The Processor — 5LoadStore Instructions Read register operands Calculate address using 1-bit offset Use ALU, but sign-extend offset Load: Read memory and update register Store: Write register value to memoryChapter 4 — The Processor — 6Branch Instructions Read register operands Compare operands Use ALU, subtract and check ero output Calculate target address Sign-extend displacement Shift left 2 places (word displacement) Add to PC + 4 Already calculated by instruction fetchChapter 4 — The Processor — 7Branch Instructionsustre-routes wiresSign-bit wire replicatedChapter 4 — The Processor — 8Composing the Elements First-cut data path does an instruction in one clock cycle Each datapath element can only do one function at a time Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructionsChapter 4 — The Processor — 9TypeLoadStore DatapathChapter 4The ProcessorChapter 4 — The Processor — 2ull DatapathChapter 4 — The Processor — 3LU Control ALU used for Load/Store: F = add Branch: F = subtract R-type: F depends on funct field§4.4 A Simple Implementation SchemeALU control Function0000 AND0001 OR0010 add0110 subtract0111 set-on-less-than1100 NORChapter 4 — The Processor — 4LU Control Assume 2-bit ALUOp derived from opcode Combinational logic derives ALU controlopcode ALUOp Operation funct ALU function ALU controllw 00 load word  add 0010sw 00 store word  add 0010beq 01 branch equal  subtract 0110R-type 10 add 100000 add 0010subtract 100010 subtract 0110AND 100100 AND 0000OR 100101 OR 0001set-on-less-than 101010 set-on-less-than 0111Chapter 4 — The Processor — 5The Main Control Unit Control signals derived from instruction0 rs rt rd shamt funct1:2 :02:21 20:1 1:11 10: or 4 rs rt address1:2 2:21 20:1 1:04 rs rt address1:2 2:21 20:1 1:0R-typeLoad/StoreBranchopcode always readread, except for loadwrite for R-type and loadsign-extend and addChapter 4 — The Processor — 6Datapath ith ControlChapter 4 — The Processor — 7Type InstructionChapter 4 — The Processor — 8Load InstructionChapter 4 — The Processor — 9BranchonEqual InstructionChapter 4 — The Processor — 10ControllerR-format Iw sw beqOp0Op1Op2OpOp4OpInputsOutputsRegDstALUSrcMemtoRegRegWriteMemReadMemWriteBranchALUOp1ALUOpOR-format lw sw beqOpcode000000 100011 101011 000100OutputsRegDst 1 0  ALUSrc 0 1 1 0MemtoReg 0 1  RegWrite 1 1 0 0MemRead 0 1 0 0MemWrite 0 0 1 0Branch 0 0 0 1ALUOp1 1 0 0 0ALUOp2 0 0 0 1Chapter 4 — The Processor — 11Implementing umps ump uses word address Update PC with concatenation of op 4 bits of old PC 2-bit jump address 00 Need an extra control signal decoded from opcode2 address1:2 2:0umpChapter 4 — The Processor — 12Datapath ith umps ddedChapter 4 — The Processor — 13 Pipelined Implementation Why isn’t single cycle enough? control is relatively simple CPI is 1, but cycle time must be long enough for every instruction to complete branch instruction versus load instruction loads require instruction fetch, register access, ALU, memory access, register access branches require instruction fetch, register access, ALU and this is for a simplified processor no floating point ops, no multiply or divideUp