4_84_94_104_11Chapter 4The ProcessorHazards Suppose initially, register $i holds the number 2i What happens when we see the following dynamic instruction sequence: add $3, $10, $11 this should add 20 + 22, putting result 42 into $3 lw $8, 50($3) this should load memory location 92 (42+50) into $8 sub $11, $8, $7  this should subtract 14 from that just-loaded valueThe Pipeline in Executionlw $8, 50($3)add $3, $10, $11 Execute/Address CalculationMemory Access Write BackInstructionmemoryAddress4320AddAddresultShiftleft 2IF/ID EX/MEM MEM/WBMux01AddPC0WritedataMux1RegistersReaddata 1Readdata 2Readregister 1Readregister 216SignextendWriteregisterWritedataReaddata1ALUresultMuxALUZeroID/EXDatamemoryAddress2022The Pipeline in Executionsub $11, $8, $7 lw $8, 50($3) add $3, $10, $11 Memory Access Write BackInstructionmemoryAddress4320AddAddresultShiftleft 2IF/ID EX/MEM MEM/WBMux01AddPC0WritedataMux1RegistersReaddata 1Readdata 2Readregister 1Readregister 216SignextendWriteregisterWritedataReaddata1ALUresultMuxALUZeroID/EXDatamemoryAddress20224261650HAZARD: This should have been “42”!But register 3 didn’t get updated yet.The Pipeline in Executionadd $10, $1, $2 sub $11, $8, $7 lw $8, 50($3) add $3, $10, $11 Write BackInstructionmemoryAddress4320AddAddresultShiftleft 2IF/ID EX/MEM MEM/WBMux01AddPC0WritedataMux1RegistersReaddata 1Readdata 2Readregister 1Readregister 216SignextendWriteregisterWritedataReaddata1ALUresultMuxALUZeroID/EXDatamemoryAddress650161456And this should be a valuefrom memory (which hasn’teven been loaded yet).Recall: this shouldhave been “92”42Chapter 4 — The Processor — 6Hazards Situations that prevent starting the next instruction in the next cycle Structure hazards A required resource is busy Data hazard Need to wait for previous instruction to complete its data read/write Control hazard Deciding on control action depends on previous instructionChapter 4 — The Processor — 7Structure Hazards Conflict for use of a resource In MIPS pipeline with a single memory Load/store requires data access Instruction fetch would have to stall for that cycle Would cause a pipeline “bubble” Hence, pipelined datapaths require separate instruction/data memories Or separate instruction/data cachesChapter 4 — The Processor — 8Data Hazards An instruction depends on completion of data access by a previous instruction add $s0, $t0, $t1sub $t2, $s0, $t3Data Hazards When a result is needed in the pipeline before it is available, a “data hazard” occurs.IM RegALUDM RegIM RegALUDMIM RegALUDM RegIM RegALUDM RegIM RegALUDM RegCC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8sub $2, $1, $3and $12, $2, $5or $13, $6, $2add $14, $2, $2sw $15, 100($2)R2 AvailableR2 NeededChapter 4The ProcessorDealing with Data Hazards In Software  insert independent instructions (or no-ops) In Hardware insert bubbles (i.e. stall the pipeline) data forwardingDealing with Data Hazards in SoftwareIM RegALUDM RegIM RegALUDM RegIM RegALUDM RegIM RegALUDM RegCC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8sub $2, $1, $3nopadd $12, $2, $5nopInsert enough no-ops (or other instructions that don’tuse register 2) so that data hazard doesn’t occur,Chapter 4 — The Processor — 4Code Scheduling to Avoid Stalls Reorder code to avoid use of load result in the next instruction C code for A = B + E; C = B + F;lw $t1, 0($t0)lw $t2, 4($t0)add $t3, $t1, $t2sw $t3, 12($t0)lw $t4, 8($t0)add $t5, $t1, $t4sw $t5, 16($t0)stallstalllw $t1, 0($t0)lw $t2, 4($t0)lw $t4, 8($t0)add $t3, $t1, $t2sw $t3, 12($t0)add $t5, $t1, $t4sw $t5, 16($t0)11 cycles13 cyclesWhere are No-ops needed? sub $2, $1,$3 and $4, $2,$5 or $8, $2,$6 add $9, $4,$2 slt $1, $6,$7 Are no-ops really necessary?Handling Data Hazards in Hardware Stall the pipelinesub $2, $1, $3add $12, $2, $5or $13, $6, $2add $14, $2, $2IM Reg DM RegIM Reg DMIM Reg DM RegIM Reg DM RegCC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8BubbleBubbleHandling Data Hazards in Hardwaresub $2, $1, $3add $12, $3, $5or $13, $6, $2add $14, $12, $2IM Reg DM RegIM Reg DMIM Reg DM RegIM Reg DM RegCC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8Bubble Bubblesw $14, 100 ($2)RegIM RegDMCC9CC10CC11BubblePipeline Stalls To insure proper pipeline execution in light of register dependences, we must: Detect the hazard Stall the pipeline prevent the IF and ID stages from making progress the ID stage because we can’t go on until the dependent instruction completes correctly the IF stage because we do not want to lose any instructions.The PipelineWhat comparisons tell us when to stall?PCInstructionmemoryInstructionAddInstruction[20–16]MemtoRegALUOpBranchRegDstALUSrc41632Instruction[15–0]00Mux01AddAddresultRegistersWriteregisterWritedataReaddata 1Readdata 2Readregister 1Readregister 2SignextendMux1ALUresultZeroWritedataReaddataMux1ALUcontrolShiftleft 2RegWriteMemReadControlALUInstruction[15–11]6EXMWBMWBWBIF/IDPCSrcID/EXEX/MEMMEM/WBMux01MemWriteAddressDatamemoryAddressStalling the Pipeline Prevent the IF and ID stages from proceeding don’t write the PC (PCWrite = 0) don’t rewrite IF/ID register (IF/IDWrite = 0) Insert “nops” set all control signals propagating to EX/MEM/WB to zeroChapter 4The ProcessorChapter 4 — The Processor — 2Forwarding (aka Bypassing) Use result when it is computed Don’t wait for it to be stored in a register Requires extra connections in the datapathChapter 4 — The Processor — 3Data Hazards in ALU Instructions Consider this sequence:sub $2, $1,$3and $12,$2,$5or $13,$6,$2add $14,$2,$2sw $15,100($2) We can resolve hazards with forwarding How do we detect when to forward?§4.7 Data Hazards: Forwarding vs. StallingChapter 4 — The Processor — 4Dependencies & ForwardingChapter 4 — The Processor — 5Detecting the Need to Forward Pass register numbers along pipeline e.g., ID/EX.RegisterRs = register number for Rs sitting in ID/EX pipeline register ALU operand register numbers in EX stage are given by ID/EX.RegisterRs, ID/EX.RegisterRt Data hazards when1a. EX/MEM.RegisterRd = ID/EX.RegisterRs1b. EX/MEM.RegisterRd = ID/EX.RegisterRt2a. MEM/WB.RegisterRd = ID/EX.RegisterRs2b. MEM/WB.RegisterRd = ID/EX.RegisterRtFwd fromEX/MEMpipeline regFwd fromMEM/WBpipeline regChapter 4 — The Processor — 6Detecting the Need to Forward But only if forwarding