Boise State University Electrical and Computer Engineering Department Course Syllabus for EE 230L (Section 001 & 002) Digital Systems Laboratory (1 semester credit hour) Fall 2005 Instructor: Dr. S. M. Loo Office: MEC 202E, Phone: (208) 426-5679, Email: [email protected] Office Hours: Tuesday 9-11am, Thursday 9-11am Lab Assistant: To be determined Office: MEC 311, Email: Office Hours: by appointment Course Description: Design, build, and test of small digital logic circuits using TTL gates, CMOS gates, flip-flops, registers, counters, LED, infrared LEDs, and Xilinx Spartan 3 FPGA (XC3S200). Student is required to enroll in this laboratory in the same semester with EE 230 Digital Systems. Prerequisites: COMPSCI 117 or COMPSCI 125, Co-requisite: EE230 Required text: No required text. Laboratory instructions are provided on course/laboratory webpage. Laboratory Meeting Time: Section 001: Tuesday 1:40 PM to 4:30 PM, Section 002: Thursday 6 PM to 9 PM Laboratory Meeting Location: Micron Engineering Center 311 (MEC 311) Course/Laboratory Webpage: http://coen.boisestate.edu/smloo/ee230lfall2005/ Laboratory Objectives: After taking this laboratory, the students should be able to: • Design and build the functions described by given specifications, • Analyze and simulate the functions described by logic diagrams, • Implement functions in logic gates (TTL and CMOS gates) and FPGA of given specifications, • Develop circuits using combinational and sequential components, and • Design, simulate, and implement state machine using Xilinx ISE, Modelsim Xilinx Edition, and Spartan 3 Starter Kit. Grading: 10 Laboratory Assignments 60% 2 Hands-on Quizzes 20% Final Project 20% Grade determination: 100%-90% = A, 89%-80% = B, 79%-70% = C, 69%-60% = D, < 60% = F Pre-Labs and Lab Reports: You are required to turn-in pre-lab for the current week’s laboratory assignment as well as the lab report for the previous week’s assignment. Even though you are working in team of two (see team assignment), each student is required to turn-in or show the Lab Instructor your individual pre-lab. The pre-lab is required to be completed before the start of practical laboratory assignment. Otherwise you will not have enough time to finish the entire lab. If a team consistently (two chances are given) coming to the lab without completing the pre-lab, the Lab Instructor will not allow that team to carry on the practical portion of that laboratory assignment. The Lab Report is a collaborative effort between you and your lab partner. One week is given to complete the write-up.Final Project: See the course/laboratory website for project description. This project will not be completely defined. We will go through a few negotiation sessions. You get to ask all the questions you want. Schedule of Laboratory Assignments: Week Lab Laboratory Topic Details (Just a little bit more! See lab write-up) 1 No Lab 2 0 Basic and Tutorial: Introduction to Digital Systems Introduction to discrete logic prototyping board, logic components, and Xilinx ISE and Modelsim Xilinx Edition). Implement functions in logic gates on discrete logic prototyping board with 7400 series chips. 3 1 Combinational Circuits: Universal NAND Build basic logic with just NAND and NOR. Design & Simulate with Xilinx and Modelsim. Build circuits on Proto-Board with 7400 series chips. 4 2 Advanced Combinational Circuits: "Bad" Logic Circuit Re-Design Derive Boolean expression from existing circuit. Simplify output equation. Re-design circuit of simplified equation. 5 3 Introduction to FPGA: Mystery Chip Design Derive Boolean expression from truth table. Design & Simulate in Xilinx. Implement circuits and test their functionality with FPGA. 6 4 Adders & Subtracters: Arithmetic Unit Modular Design. Design a 4-bit adder by using 1-bit full adder modules. Build an adder/substract unit with add/sub control bit. Test on FPGA. 7 Lab Quiz #1 Derive: Truth Table, K-Map, Simplify Expressions, Design Circuit, Timing Diagram/Simulation, Test on FPGA Platform. 8 5 Multiplexer, Encoder, Decoder: Multiplexer and Decoders Design simple MUXs & Decoders with logic gates. Implement certain Boolean Expressions with MUXs and decoders. 9 6 Adders & Multipliers: Yet Another Arithmetic Unit Design 4-bit fast adders & multipliers. Multiplex signals from multiple sources into one common data bus. 10 7 VHDL, Latches & Flip Flops: VHDL & Simple "Memory" Circuit Design a logic circuit using VHDL instead of Schematic Capture in Xilinx. Understand/show the differences between latch and flip-flop. 11 Spring Break 12 8 Counters: Latch, Flip-Flop, Up-Down Counter Design a 4-bit up-down counter and download the design to FPGA 13 9 Finite State Machines: Sequence Detector Design a state-machine sequence detector. Show state diagram, state table and assignment table, K-maps, equations, logic circuit, download design to FPGA. 14 Lab Quiz #2 Design a state-machine sequence detector. Show state diagram, state table and assignment table, K-maps, equations, logic circuit, download design to FPGA. 15 Final Project See course/laboratory website for