DOC PREVIEW
BOISE STATE EE 230L - Lab 3: “Bad” Logic Circuit Re-Design

This preview shows page 1 out of 2 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 2 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 2 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

Boise State University Digital Systems Laboratory Electrical and Computer Engineering Department EE230L Page 1 of 2 Spring 2007 Lab 3: “Bad” Logic Circuit Re-Design Objective: Redesign a “bad” circuit You’ve been hired by a company to re-design an electronic circuit used in a product sold by the company. The boss’ son did the original circuit design. He has produced no documentation for this design and others have found the design to be sloppy. The only information available is the attached schematic that is used in the assembly area. The test engineer had found that the product consumes too much power, and takes up too much space. However, the friendly criticism didn’t result in any action to be taken. The boss has indicated that the anticipated sales volume for the product doesn’t justify custom silicon, which suggests that off-the-shelf chips are his preferred solution (For this lab, “off-the-shelf” chips are represented by the standard chips in the BSU TTL library.). It is rumored that a competing company is going to introduce a similar device, so minimizing the number of components to construct the device in order to reduce the cost is a very important goal. The boss is extremely busy and has a short attention span, so you will need to present your re-design very clearly and concisely in a document that he can read while he is driving to work (Remember, your job is on the line!). Since the boss often has questions about the details, calculations and other detailed data to support your conclusions need to be included in an appendix. The following list is your laboratory work: 1. Derive the Boolean expression for the output function from the logic circuit given, 2. Simplify the output function by whatever means you are comfortable, 3. Draw the schematic for the simplified expressions, 4. Use the Xilinx ISE and Modelsim to perform a simulation to verify the design, 5. Re-implement the simplified circuit using only NAND gates and simulate, and 5. Build the NAND only implementation on your proto-board. Report: Record all results in your team report. Some of the important items are: 1. The original and simplified Boolean expressions, 2. The original and simplified truth table, 3. Simplification technique(s), 4. Type and number of chips used, 5. Schematic diagram, 6. Simulation waveform, 7. Results and reflections, and 8. Include schematics and simulation waveforms for all implementations.Boise State University Digital Systems Laboratory Electrical and Computer Engineering Department EE230L Page 2 of 2 Spring 2007 Figure 1. “Bad” logic circuit. You should inform the lab instructor that you have completed all of the above and ready for the following. Getting Ready for Lab 4 -- Mystery Chip You will be programming the Spartan-3 Starter Kit with a given bit file. You are required to record the behavior (truth table) of the design and describe what the designs embedded in the bit file does! All the I/Os will be given. Derive and implement the necessary steps to determine the functionality of the given mystery chip. Report: Record your procedures in your report and the solution to the mystery


View Full Document

BOISE STATE EE 230L - Lab 3: “Bad” Logic Circuit Re-Design

Download Lab 3: “Bad” Logic Circuit Re-Design
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Lab 3: “Bad” Logic Circuit Re-Design and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lab 3: “Bad” Logic Circuit Re-Design 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?