BOISE STATE EE 230L - Lab 2: “Bad” Logic Circuit Re-Design

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Boise State University Digital Systems Laboratory Electrical and Computer Engineering Department EE230L Page 1 of 2 Spring 2005 Lab 2: “Bad” Logic Circuit Re-Design Objective: Redesign a “bad” circuit You’ve been hired by a company to re-design an electronic circuit used in a product sold by the company. The boss’ son did the original circuit design. He has produced no documentation for this design and others have found the design to be sloppy. The only information available is the attached schematic that is used in the assembly area. The test engineer had found that the product consumes too much power, and takes up too much space. However, the friendly criticize didn’t resulted any action to be taken. The boss has indicated that the anticipated sales volume for the product doesn’t justify custom silicon, which suggests that off-the-shelf chips are his preferred solution (For this lab, “off-the-shelf” chips are represented by the standard chips in the BSU TTL library.). It is rumored that a competing company is going to introduce a similar device, so minimizing the number of components to construct the device in order to reduce the cost is a very important goal. The boss is extremely busy and has a short attention span, so you will need to present your re-design very clearly and concisely in a document that he can read while he is driving to work (Remember, your job is on the line!). Since the boss often has questions about the details, calculations and other detailed data to support your conclusions need to be included in an appendix. Pre-Lab: 1. Derive the Boolean expression for the output function from the logic circuit given, 2. Simplify the output function by whatever means you are comfortable, 3. Draw the schematic for the simplified expressions, 4. Use the Xilinx ISE and Modelsim to perform a simulation to verify the design, 5. Re-implement the simplified circuit using only NAND gates and simulate, and 6. Re-implement the simplified circuit using only NOR gates and simulate. In-Lab: 1. Build the NAND only implementation on your proto-board. Report: Record all results in your team report. Some of the important items are: 1. The original and simplified Boolean expressions, 2. The original and simplified truth table, 3. Simplification technique(s), 4. Type and number of chips used, 5. Schematic diagram, 6. Simulation waveform, 7. Results and reflections, and 8. Include schematics and simulation waveforms for AND-OR and NOR-NOR implementations as appendix.Boise State University Digital Systems Laboratory Electrical and Computer Engineering Department EE230L Page 2 of 2 Spring 2005 Figure 1. “Bad” logic


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BOISE STATE EE 230L - Lab 2: “Bad” Logic Circuit Re-Design

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