Introduction to Computer Engineering CS ECE 252 Fall 2009 Prof Mark D Hill Computer Sciences Department University of Wisconsin Madison Chapter 5 The LC 3 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Instruction Set Architecture ISA All of the programmer visible components and operations of the computer memory organization address space how may locations can be addressed addressibility how many bits per location register set how many what size how are they used instruction set opcodes data types addressing modes ISA provides all information needed for someone that wants to write a program in machine language or translate from a high level language to machine language 5 3 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display LC 3 Overview Memory and Registers Memory address space 216 locations 16 bit addresses addressability 16 bits Registers temporary storage accessed in a single machine cycle accessing memory generally takes longer than a single cycle eight general purpose registers R0 R7 each 16 bits wide how many bits to uniquely identify a register other registers not directly addressable but used by and affected by instructions PC program counter condition codes 5 4 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display LC 3 Overview Instruction Set Opcodes 15 opcodes Operate instructions ADD AND NOT Data movement instructions LD LDI LDR LEA ST STR STI Control instructions BR JSR JSRR JMP RTI TRAP some opcodes set clear condition codes based on result N negative Z zero P positive 0 Data Types 16 bit 2 s complement integer Addressing Modes How is the location of an operand specified non memory addresses immediate register memory addresses PC relative indirect base offset 5 5 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Operate Instructions Only three operations ADD AND NOT Source and destination operands are registers These instructions do not reference memory ADD and AND can use immediate mode where one operand is hard wired into the instruction Will show dataflow diagram with each instruction illustrates when and where data moves to accomplish the desired operation 5 6 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display NOT Register Note Src and Dst could be the same register 5 7 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display ADD AND Register this zero means register mode 5 8 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display ADD AND Immediate this one means immediate mode Note Immediate field is sign extended 5 9 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Using Operate Instructions With only ADD AND NOT How do we subtract How do we OR How do we copy from one register to another How do we initialize a register to zero 5 10 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Data Movement Instructions Load read data from memory to register LD PC relative mode LDR base offset mode LDI indirect mode Store write data from register to memory ST PC relative mode STR base offset mode STI indirect mode Load effective address compute address save in register LEA immediate mode does not access memory 5 11 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display PC Relative Addressing Mode Want to specify address directly in the instruction But an address is 16 bits and so is an instruction After subtracting 4 bits for opcode and 3 bits for register we have 9 bits available for address Solution Use the 9 bits as a signed offset from the current PC 9 bits 256 offset 255 Can form any address X such that PC 256 X PC 255 Remember that PC is incremented as part of the FETCH phase This is done before the EVALUATE ADDRESS stage 5 12 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display LD PC Relative 5 13 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display ST PC Relative 5 14 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Indirect Addressing Mode With PC relative mode can only address data within 256 words of the instruction What about the rest of memory Solution 1 Read address from memory location then load store to that address First address is generated from PC and IR just like PC relative addressing then content of that address is used as target for load store 5 15 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display LDI Indirect 5 16 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display STI Indirect 5 17 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Base Offset Addressing Mode With PC relative mode can only address data within 256 words of the instruction What about the rest of memory Solution 2 Use a register to generate a full 16 bit address 4 bits for opcode 3 for src dest register 3 bits for base register remaining 6 bits are used as a signed offset Offset is sign extended before adding to base register 5 18 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display LDR Base Offset 5 19 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display STR Base Offset 5 20 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Load Effective Address Computes address like PC relative PC plus signed offset and stores the result into a register Note The address is stored in the register not the contents of the memory location 5 21 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display LEA Immediate 5 22 Copyright The McGraw Hill Companies Inc Permission required for reproduction or display Example Address Instruction Comments x30F6 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 R1 PC 3 x30F4 x30F7 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 R2 R1 14 x3102 x30F8 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 M PC 5 R2 M x30F4 x3102 x30F9 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2 0 x30FA 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 R2 R2 5 5 x30FB 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 M R1 14 R2 M x3102 5 x30FC 1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 R3 M M x30F4 R3 M x3102 R3 5 opcode 5 23 Copyright The McGraw Hill Companies Inc Permission required for