Latches Flip flops Computer Architecture CS 215 1 Sequential Circuits Inputs Storage Elements Storage elements Combinat ional Logic State Outputs Next State Latches or Flip Flops Combinatorial Logic 2 Sequential Circuits Inputs Storage Elements Combinatorial Logic Next state function Next State f Inputs State Output function Mealy Outputs g Inputs State Output function Moore Outputs h State Output function type depends on specification and affects the design significantly Combinat ional Logic State Outputs Next State 3 Sequential Circuits Synchronous Behavior defined from knowledge of its signals at discrete instances of time Storage elements observe inputs and can change state only in relation to a timing signal clock pulses from a clock Asynchronous Behavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change If clock just regarded as another input all circuits are asynchronous Nevertheless the synchronous abstraction makes complex designs tractable 4 Discrete Event Simulation Rules Gates modeled by an ideal instantaneous function and a fixed gate delay Any change in input values is evaluated to see if it causes a change in output value Changes in output values are scheduled for the fixed gate delay after the input change At the time for a scheduled output change the output value is changed along with any inputs it drives 5 Simulated NAND Gate A DELAY 0 5 ns B t ns A B 1 1 0 1 0 1 0 1 0 5 0 8 1 0 1 0 13 Example A 2 Input F Instantaneous 1 1 F I 0 1 0 F 0 0 1 1 0 1 0 1 0 1 0 F NAND gate with a 0 5 ns delay Assume A and B have been 1 for a long time At time t 0 A changes back to 1 to a 0 at t 0 8 ns Comment A B 1 for a long time F I changes to 1 F changes to 1 after a 0 5 ns delay F Instantaneous changes to 0 F changes to 0 after a 0 5 ns delay 6 Basic NAND S R Latch S set Cross Q Coupling two NAND gates gives the S R Latch S 0 R 0 is forbidden as input pattern Q R reset Time R S Q Q Comment 1 1 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 1 Stored state unknown Set Q to 1 Now Q remembers 1 Reset Q to 0 Now Q remembers 0 Both go high Unstable 7 Basic NOR S R Latch R reset Crosscoupling two NOR gates Time R gives 0 the 0 S R 0 Latch 1 0 1 0 S set S 0 1 0 0 0 1 0 Q 1 1 0 0 0 Q 0 0 1 1 0 Q Q Comment Stored state unknown Set Q to 1 Now Q remembers 1 Reset Q to 0 Now Q remembers 0 Both go low Unstable 8 Clocked S R Latch Adding two NAND S gates to the basic S R NAND latch C gives the clocked S R latch R Q Q Has a time sequence behavior similar to the basic S R latch except that the S and R inputs are only observed when the line C is high C means control or clock 9 Clocked S R Latch The Clocked S R Latch can be described by a table S Q Q t S R C Q R The table describes what happens after the clock at time t 1 based on current inputs S R and current state Q t 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q t 1 0 0 1 1 0 1 Comment No change Clear Q Set Q Indeterminate No change Clear Q Set Q Indeterminate 10 D Latch D Q Adding an inverter to the S R Latch C gives the D Latch Note that there are no indeterminate states Q 0 0 1 1 D 0 1 0 1 Q t 1 0 1 0 1 Comment No change Set Q Clear Q No Change Q The graphic symbol for a D Latch is D Q C Q 11 Flip Flops Master slave flip flop Edge triggered flip flop Standard symbols for storage elements 12 S R Master Slave Flip Flop Two clocked S S C C Q S Q Q C S R latches in series R R Q with the clock on the R Q Q second latch inverted The input is observed by the first latch with C 1 The output is changed by the second latch with C 0 The path from input to output is broken by the difference in clocking values C 1 and C 0 The behavior demonstrated by the example with D driven by Y given previously is prevented since the clock must change from 1 to 0 before a change in Y based on D can occur 13 Edge Triggered D Flip Flop The edge triggered D flip flop is the same as the masterslave D flip flop D D Q S Q Q Q Q C C C Q R It can be formed by Replacing the first clocked S R latch with a clocked D latch or Adding a D input and inverter to a master slave S R flip flop The delay of the S R master slave flip flop can be avoided since the 1s catching behavior is not present with D replacing S and R inputs The change of the D flip flop output is associated with the negative edge at the end of the pulse It is called a negative edge triggered flip flop 14 Positive Edge Triggered D Flip Flop Formed by adding inverter to clock input D D Q S Q Q Q Q C C C Q R Q changes to the value on D applied at the positive clock edge within timing constraints to be specified Our choice as the standard flip flop for most sequential circuits 15 Standard Symbols for Storage Elements S S D D R R C C D with 0 Control D with 1 Control SR a Latches SR Master Slave Postponed outputS C indicators S Dynamic indicator D C C C R Edge Triggered D R Triggered SR Triggered SR Triggered D Triggered D b Master Slave Flip Flops D D C C Triggered D Triggered D c Edge Triggered Flip Flops 16 State Diagrams The sequential circuit function can be represented in graphical form as a state diagram with the following components A circle with the state name in it for each state A directed arc from the Present State to the Next State for each state transition A label on each directed arc with the Input values which causes the state transition and A label On each circle with the output value produced or On each directed arc with the output value produced 17 State Diagrams Label form On circle with output included …