Processor Design Computer Architecture CS 215 Updated 10 21 14 Registers Special purpose registers Accumulators arithmetic registers Status register Machine Types Accumulator machines Limited number of data accumulators 1 address machines Stack machines No register names Registers organized as a stack 0 address machine General register machines Most often used today Registers used for almost any purpose Instruction Sets Each family of CPUs has its own instruction set Instruction codes are mapped to instructions Data movement Arithmetic Logic Control Instructions Must contain Which operation to perform Where to find the operand s if any Where to put the result if any Where to find the next instruction Memory Access Each register has a unique address Two operations Read Write Memory Access Read CPU places an address on the address bus and a read request on the control bus Memory unit receives request decodes address and locate data at address Memory unit places data on data bus Memory unit places a complete message on control bus Memory Access Write CPU places an address on the address bus value to be written on data bus and a write request on the control bus Memory unit receives request decodes address Memory unit stores data at address Memory unit places a complete message on control bus Addressing Modes Immediate i Direct M i Indirect M M i Register direct R i Register indirect M R i Displacement M R i c Relative M PC c SRC Instructions Load instructions ld ldr la lar Store instructions st str Arithmetic add addi sub neg Logic and andi or ori not shr sha shl shc Branching br brl Miscellaneous nop stop Instruction Formats ld st la addi andi ori 31 27 26 Op 22 21 ra 17 16 12 11 rb 4 2 0 4 2 0 c2 ldr str lar 31 27 26 Op 22 21 ra 17 16 12 11 c1 Instruction Formats neg not 31 27 26 Op 22 21 ra 17 16 unused 12 11 rc 4 2 0 4 2 0 unused br 31 27 26 Op 22 21 unused 17 16 rb 12 11 rc c3 unused Cond Instruction Formats brl 31 27 26 Op 22 21 ra 17 16 rb 12 11 rc 4 c3 unused 2 0 Cond add sub and or 31 27 26 Op 22 21 ra 17 16 rb 12 11 rc 4 unused 2 0 Instruction Formats shr shra shl shc 31 27 26 Op 31 22 21 ra 27 26 Op 17 16 12 11 rb 22 21 ra 4 c2 17 16 rb unused 12 11 rc Count 4 c3 unused 2 0 2 0 00000 nop stop 31 27 26 Op 22 21 17 16 12 11 unused 4 2 0 cnt equ org seq dc next dc ans dw org lar la la loop ld ld add st addi addi brnz stop Example 8 0 1 1 cnt 0x1000 r31 loop r0 cnt r1 seq r2 seq r1 r3 next r1 r2 r2 r3 r2 ans r1 r1 r1 4 r0 r0 1 r31 r0 Try this Develop instruction formats for a 16 bit CPU which has 16 16 bit general purpose registers CPU Design Control Unit Generates the control signals in the correct order to effect the correct data path activity Data Path Set of interconnections and auxiliary registers Needed to accomplish overall changes an instruction makes CPU Control Unit Control signals out Data Path Control unit inputs Register Transfer Notation Provides a formal means of describing machine structure and function Is at the just right level for machine descriptions Does not replace hardware description languages Can be used to describe what a machine does an Abstract RTN without describing how the machine does it Can also be used to describe a particular hardware implementation A Concrete RTN RTN Cont d At first you may find this meta description confusing because it is a language that is used to describe a language You will find that developing a familiarity with RTN will aid greatly in your understanding of new machine design concepts We will describe RTN by using it to describe SRC Static Properties Specifying registers IR 31 0 specifies a register named IR having 32 bits numbered 31 to 0 Naming using the naming operator op 4 0 IR 31 27 specifies that the 5 msbs of IR be called op with bits 4 0 Notice that this does not create a new register it just generates another name or alias for an already existing register or part of a register Dynamic Properties Conditional expressions op 12 R ra R rb R rc if condition then defines the add instruction RTN Assignment Operator This fragment of RTN describes the SRC add instruction It says when the op field of IR 12 then store in the register specified by the ra field the result of adding the register specified by the rb field to the register specified by the rc field Register Declarations General register specifications shows some features of the notation Describes a set of 32 32 bit registers with names R 0 to R 31 R 0 31 31 0 Name of registers Register in square brackets msb specifies a range of indices lsb Bit in angle brackets Colon separates statements with no ordering Naming Operator Defining names with formal parameters is a powerful formatting tool Used here to define word memory big endian M x 31 0 Mem x Mem x 1 Mem x 2 Mem x 3 Dummy parameter Naming operator Concatenation operator All bits in register if no bit index given Memory Processor State PC 31 0 32 bit register Program Counter IR 31 0 32 bit register Instruction Register Run 1 bit run halt indicator Strt Start signal R 0 31 31 0 32 32 bit general purpose registers Main Memory Mem 0 232 1 7 0 232 addressable bytes of memory M x 31 0 Mem x Mem x 1 Mem x 2 Mem x 3 Instruction Formats op 4 0 IR 31 27 Operation code field ra 4 0 IR 26 22 Target register field rb 4 0 IR 21 17 Operand address index or branch target register rc 4 0 IR 16 12 Second operand conditional test or shift count register Instruction Formats c1 21 0 IR 21 0 Long displacement field c2 16 0 IR 16 0 Short displacement or immediate field c3 11 0 IR 11 0 Count or modifier field Effective Address Calculations Displacement disp 31 0 rb 0 c2 16 0 sign extend rb 0 R rb c2 16 0 sign extend 2 s compliment Relative rel 31 0 PC 31 0 c1 21 0 sign extend 2 s comp Instruction Interpretation Execution instruction interpretation Run Strt Run 1 instruction intepretation Run IR M PC PC PC 4 instruction execution Load Store Instructions instruction execution ld op 1 R ra M disp ldr op 2 R ra M rel st op 3 M disp R ra str op 4 M rel R ra la op 5 R ra disp load register load register relative store register store register relative load displacement address lar op 6 R ra …