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GT ECE 4420 - Overview of ECE4420: Digital CMOS circuits

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Overview of ECE4420: DigitalCMOS circuitsSpring 2007Prof. Jeff DavisTo analyze, design, andsimulate high-speed, low-area, and/or low-powerdigital circuits.What is the goal of this class?What Is This Trend Called?10001001010.10.010.001197019801990200020102020MillionTransistorsWhat drives Moore’s Law?n+ n+pSource DrainGateM(etal) O(xide)S(emiconductor)toxL FVddDevice Scaling and Price per Function!Cost Per FunctionSmaller Transistor size reduces the Cost-Per-Function!Impact of Moore’s Law10001001010.1Power(Watts)1970 1980 1990 2000 2010 2020Unsustainable trend!YearSource: K. Bowman, Impact of Variation sources on Circuit Performance and Design Techniques for Variation Tolerence,Presentation for Georgia Tech Seminar, April 18, 2006.Leakage Power is GROWING!Source: K. Bowman, Impact of Variation sources on Circuit Performance and Design Techniques for Variation Tolerence,Presentation for Georgia Tech Seminar, April 18, 2006.50%40%30%20%10%0%1.50.70.350.180.090.05Technology (microns)Leakage Power (% of total)Interconnect IssuesTechnology Generation MOSFET Switching Delay RC delay of a 1 mm interconnect MOSFET switching energy Switching Energy of a 1mm interconnect 1 micron 20ps 1ps 300fJ 400fJ 100nm 5ps 30ps 2fJ 10fJ 35nm 2.5ps 250ps 0.1fJ 3fJ  Rwire=!WH!Lwire Cwire=!r!oWH!LwireWHρHε != RwireCwire="r"o#Lwire2H#H"A few other trendsMark Bohr, Intel Fellow, 2002 Press Release www.intel.comTopics in this class• Technology Overview– Silicon Run• MOSFET Models– Threshold Voltage (Bulk MOSFET)– Basic Square Law Model– Sources of Leakage Currents– Linear Resistive Models– Estimation of Capacitance From LayoutTopics in this class• CMOS Inverter– DC Voltage Transfer Characteristics– Noise Margins– Propagation Delay/ Low to High Transitions– Static and Dynamic Power Estimation• HSPICE Simulation• Application– Cascaded Driver Design– Global Interconnect Repeater Design• RC interconnect modelsTopics in this class• CMOS Static Gates– Relative Sizing– Noise Margins– Propagation Delay Estimations– Tristate Circuits– Schmitt Trigger Circuits• Static Circuit Alternatives– Mirror Circuits– Pseudo NMOS Circuits– Pass Gate & Transmission Gate DesignTopics in this class• Dynamic CMOS Circuits– Pre-charge and Evaluate Logic– Nmos-Pmos Glitch Problem– Nmos-Pmos Dynamic Logic– Domino Logic• Keeper Circuits• Sizing Optimizations• High-Speed Cascade Techniques– Multiple Output Domino Logic (MODL)• Carry Look Ahead (CLA) application• CMOS Dual Rail Logic– Cascode Voltage Switch Logic (CVSL)– Structured Logic Trees CVSL– Dual Rail Complementary Pass Logic (CPL)Transistor & Wire MetricsCV/I MetricRC Charging TimeLong-Channel MOSFETApproximationIdsVdsDrainSourceGateVdd2)(2tddoxrodriveVVLWtI !=""µVdsIdsVgs=VddVt <Vgs<VddVgs< Vt Drive CurrentNot include: 1) Channel Length Modulation2) Mobility degradation3) Drain Induced Barrier Lowering (DIBL)4) etc…Approximate Drive CurrentMetricn+ n+pSource DrainGateM(etal) O(xide)S(emiconductor)toxL F22)(2)(2ddoxrotddoxrodriveVLWtVVLWtI!!µ!!µ"#=VddConstant-Field ScalingMOSFET device parametersScaling factor (s>1)Doping concentration (Na, Nd)sVoltage (V)1/sGate Oxide Thickness (tox) 1/sChannel Length (L)1/sTransistor Width (W)1/sJunction Depth (xj)1/s22)(2)(2ddoxrotddoxrodriveVLWtVVLWtI!!µ!!µ"#=Electric Field (E)Scaling factor (s>1)1Carrier Velocity (v = µE)1Depletion Layer Width1/sCapacitance (C=εA/tox)1/sInversion layer charge density (Qi)1Current (drift)1/sChannel Resistance (R)1Constant-Field ScalingDevice BehaviorMOSFET device parametersConstant-Field ScalingCircuit BehaviorCircuit Delay Time(τ ~ CV/I)1/sPower Dissipation per circuit (~VI)1/s2Power-Delay Product per circuit (P x τ)1/s3Circuit Density ( µ 1/A ) s2Power Density (P/A)1MOSFET device parametersScaling factor (s>1)driveICVdtdVCIdsgds=)(2)(222ddtddoxddoxdriveddVLVVLWCWLVCIVCµµ!"#==Transistor Performance Metric!!=====dddsdsVVVdsdsgttdVICdt001"( )!!"#$$%&+'(+=+=ddoxwddtddoxddwddoxdsddwgWVCLCVLVVLWCVCWLVCIVCCµµµ)2)(2)(222CgdriveICVWith Extra Wire Capacitance??Cw Rwire=!WH!Lwire Cwire=!r!oWH!Lwire != RwireCwire="r"o#Lwire2H#H"Global Wire Performance MetricWHρHεTransistor and InterconnectPerformance Metrics)(22ddVLµ!!"#$$%&+ddoxwddWVCLCVLµµ2)(222wireLHHW!"!"Smaller = Faster!Smaller = No Improvement!….Or slower!!Transistor only Transistor plus local wire Global long wireClock Frequency TrendsTrends in Clock FrequencyIntel Technology Journal Q3 1998 Thompson, Packan and Bohr2004 ITRS - Clock Frequency11010020 30 40 50 60 70 80 90 100Technology GenerationLocal Clock Frequency [Ghz]Clock Frequency DoublesEvery 3 years (tech gen)What is driving Increase in Clock Frequency? Where is extra performance coming from?1.42x performance increase every generation with device performance????2.0x increase in clock frequencyCircuit Delay Time(t ~ CV/I)1/s01020304050601985 1990 1995 2000 2005 2010YearReduction in number gates inCritical Path*Vivek De and Shekhar Borkar (INTEL), "Technology and Design Challenges for Low Power and High Performance,"1999 International Symposium on Low Power Electronics and Design, San Diego, CA, Aug. 16-17 1999, pp. 163-168.*Paul Gronowski, et al (Compact Digital), "High Performance Microprocessor Design," IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, May 1998, pp. 676-686.Average # of gate delays per clockcycleIntelAlpha1) reduced number of gates inone clock period (morepipelined)2) employing advance circuittechniquesTo maintain 2x increase in frequencyFuture Trends?Impact of multi-core


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