Fabrication of CMOS ICsECE4420Jeff Davis*Images taken from textbook: J. Uymura, “Introduction to VLSI Circuits and Systems,” John Wiley and Sons, 2002.Outline• Overview of Silicon Processing• Material Growth and Deposition• Lithography• CMOS Process FlowIntegrated Circuits created onSilicon Wafers (100-300mm)The wafer is subjected many individual processing steps to makeeach IC!!Fabrication Yield  Y =NGNT! 100%NG = Number of good working dieNT = Total number of die sitesYield enhancement is complex and time consuming!!Smaller Dies = Less costExample AMD vs. Intel:AMD Athlon XP (180nm) 129mm2(200mm wafers)Intel’s P4 (180nm) 217mm2 (200mmwafers)AMD Athlon XP (130nm) 80mm2 (200mmwafers)Intel’s P4 (130nm) 116mm2 (300mmwafers)Wafer Costs are approximatelyconstant!Outline• Overview of Silicon Processing• Material Growth and Deposition• Lithography• CMOS Process FlowThermal Oxide Growth  xsi! 0.46xoxDry vs. Wet Oxidation  Si + O2! SiO2  Si + H2O ! SiO2+ 2H2Dry Oxidation : Slow but high quality :Heat accelerates reactionWet Oxidation : Fast but high quality: Heat accelerates reactionWet/Dry Combo Example START (100) p-type 10 ohm cm wafers CLEAN in H2(S0)4-H202 piranha etch, 2 min ; clean, rinse, dry RINSE 1, 4 min RINSE 2, 4 min DRY OXIDIZE 1 hr at 1000 C in Wet Oxygen place wafers in quartz oxidation boat insert into furnace ante-chamber push at 1/2" per sec at 800 C in Oxygen ramp to 1000 C (10 C/min), 20 min turn on steam, 60 min ramp down to 800 C in Oxygen pull at 1/2" per sec unload into plastic carriersCVD Oxide ProcessDeposited SiO2 on a surface where no Si is present  SiH4(gas) + 2O2(gas) ! SiO2(solid ) + 2H2O(gas)SilaneLTO = Low Temperature Oxides!Silicon Nitride (Si3N4)• Often called nitride only• Strong barrier to most items• Use as an overglass layer to protect chip  3SiH4(gas) + 4NH3(gas) ! Si3N4(solid ) + 12H2(gas)SilaneAmmoniaSilicon NitridePolysilicon Silicon•Depositing silicon on Silicon Dioxide produces small crystallitesareas•Called poly for short•Used for gate eletrotrode in FETs•Even heavily doped this has high sheet resistance• Refractory metals (such Ti) coating on poly to decrease sheetresistance ... this is called a silicide  SiH4! Si + 2H2Silane@ 500-600 oCMetals•Aluminum vs. Copper• aluminum bulk resistivity = 2.86e-6 Ω-cm• copper bulk resistivity = 1.67e-6 Ω-cm•Electromigration•Current flow displace metal ions in metalsdenthigh-current density moves the dent!High current densityHigh current densityElectromigrationDesign Rules limit current densityDoping Silicon Layersselective doping is very important!!Ion ImplantationBoron Triflouride (BF3)Ion Sourcemagnetwafer targetIon ImplantationThe Ion Stopping Process100-200 KeVPhysics 101: One electron-volt is equal to the amount of energy gained by an electron dropping through a potential difference of one volt, which is 1.6 ´ 10-19 joules •Ion energies control depth•Can penetrate thin oxide layers•Damage can result,but is fixedwith an moderate heated (i.e.annealing)Gaussian Implant ProfileProjected RangeStraggle  Nion(x ) = Npe!12x!Rp"Rp# $ % % & ' ( ( 2Chemical Mechanical Polish(CMP)Epitaxial Layer Growth (EPI)Trichlorosilane (TCS) @ 1000-1180 oCSource: www.semiconductorfabtech.com/journals/ edition.15/ft15.pdfs/ft15_215.pdfOutline• Overview of Silicon Processing• Material Growth and Deposition• Lithography• CMOS Process FlowPhoto = light!Excimer Laser Sources• (250-130nm)Krypton Fluoride (KrF) 248nm• (90nm) Argon Fluoride ArF (193nm)• (65nm?) Fluorine F2 (157nm)Reticle or Mask DefinitionRemember: During Layout using CAD tools this is whatyou are designing!!!Photoresist ApplicationExposure StepCharacteristics of positivephotoresistNegative photoresist works in opposite way!!Etching an Oxide LayerReactive Ion EtchingRIE Etching uses both ion bombardment and chemicalreaction etching!!!**Source: www.atechsystem.co.kr/custom/rie.pdfReactive Ion Etch (RIE)Anisotropic Etch**Source: www.atechsystem.co.kr/custom/rie.pdfNo undercut!Ion Implantation of Doped SiPatternsnote: lateral dopingStep-and-Repeat Processregistration targets for alignment betweenmasking steps!Clean Room Definitions•Use HEPA filters that are 99.97% effective of removing particlesthat are 0.5microns or larger.•Class X clean rooms means that there are less than X particles percubic foot with diameter greater than 0.5 micron•Typical clean room facilities have various class levels•e.g. TSMC Fab 6 (190,000sqft 32,000 wafer-per-month)•Class 100 ballroom has Class 0.1 SMIF minienviromentsOutline• Overview of Silicon Processing• Material Growth and Deposition• Lithography• CMOS Process FlownWell and Active Area MaskingStepsnWell MaskActive Area MaskNeeded to define oxide electrical isolation between devices!nFET and pFET will eventually go here!Field Oxide (FOX) growthField Oxide needed to define oxide electrical isolation between devices!Self-Aligned Gate ProcessPoly MaskGate/Drain/Source Regions are automatically alignedSelf-Aligned Gate ProcesspSelect MasknSelect Maskp+ gate electroden+ gate electrodeSource/Drain ContactsActive Contact MaskPoly Contact MaskMetal Masking StepsMetal 1 Mask Via Mask Metal 2 MaskBonding Pad StructureLightly Doped Drain (LDD)nFETOxide etch to create sidewallspacers (no additional maskneeded)Lightly Doped Drain (LDD)nFETOxide etch to create sidewallspacers (no additional maskneeded)Silicides•Reduce sheet resistance of gate from 25 Ω to 10s mΩ!!•Defined as a refractory metal(e.g. Ti,Ta,Pt, etc) coatedover silicon or polysilicon Silicide reduces contact resistance of Tungsten ContactCopper Interconnect: DamasceneCopper needs a barrier layer (e.g. TiN) to block diffusion to SiO2!Dual-Damascene ProcessCopper vias ...1) lower resistance than Tungsten2) Electromigration