EE40 Homework #5 Due Wednesday, May 18th 1:00pm Office Hours: Luke Guo ([email protected]): Monday 4:00pm – 6:00pm, Moore 239 Alexander Hu ([email protected]): Monday 9:45pm – 11:45pm, Moore 139 Hyung Wan ([email protected]): Tuesday 9:00pm – 11:00pm, Moore 139 Important: all problems to be solved for room-temperature (300K), and under equilibrium. Tables of fundamental constants and properties of select semiconductors are available on the class website and should be used when required values are not explicitly stated in the question. 1. [50%] Revisit of NPN BJT We have a silicon bipolar transistor at T=300K given the following parameters: Donor concentration in the emitter: NE=1*1018 cm-3 Acceptor concentration in the base: NB=1*1016 cm-3 Donor concentration in the collector: NC=2*1015 cm-3, Diffusion constant of holes in the emitter DE=10cm2/sec, Diffusion constant of holes in the collector DC=40cm2/sec, Diffusion constant of electrons in the base DB=25cm2/sec, Holes lifetime in the emitter: τEo=10-7sec Holes lifetime in the collector: τCo=10-5sec Electrons lifetime in the base τB0= 10-7sec, Distance between the base-emitter junction and the base-collector junction: W=0.7µm (a) Calculate the width of the quasi-neutral region of the base with VBE=0.65 Volt and VCB=1 Volt (b) Calculate the common emitter current gain (β) for the same biasing voltages, using the same assumptions as in the notes. (c) Calculate the change in width of the quasi-neutral region of the base with VCB changing from VCB=2Volts to VCB=10 Volts. (d) Calculate Jc(VCB=2 Volts) and Jc(VCB=10 Volts), for VBE=0.65 Volt (e) Derive the expression of CEJcV∂∂ when VBE is constant. Why is that parameter important in circuits? (f) Calculate the “Early voltage” AV, defined by: CCCE CE AIIV VV∆=∆+. (CEV∆, and cI∆ are the changes in collector-emitter voltage and collector current for 8CBV Volt∆=). Use VBE=0.65 Volt.2. [25%] Flat-band voltage [a] Consider a n+ polysilicon/silicon dioxide/n-type silicon MOS structure. Let Nd=4x1015 cm-3. Calculate the ideal flat-band voltage for tox=20nm. (5%) [b] Considering the results of part [a], determine the shift in flat-band voltage for (i) Qss’=4x1010 cm-2 and (ii) Qss’=1x1011 cm-2. (10%) [c] repeat part [a] and [b] for an oxide thickness of tox=12nm. (10%) 3. [25%] MOS band diagrams and threshold voltage Consider a MOS capacitor with an n+ polysilicon gate and n-type silicon substrate. Assume Na=1x1016 cm-3 and let Ef-Ec= 0.2eV in the n+ polysilicon. Assume the oxide has a thickness of tox=30nm. Also assume that χ’(polysilicon) = χ’(single crystal silicon). [a] Sketch the energy-band diagrams (i) for VG=0 and (ii) at flat band. (10%) [b] Calculate the metal-semiconductor work function difference. (5%) [c] Calculate the threshold voltage for the ideal case of zero fixed oxide charge and zero interface states. The threshold voltage is defined as the applied gate voltage required to achieve the inversion point, where ϕs=2 ϕfn.