EE40 CCD Lecture v2.pdfEE40 CCD Lecture v2.pdfCharge-Coupled DevicesQuick Review of MOS JunctionsEnergy Band Diagram (Ideal MOS Diodes)Charge, Field, & Potential at InversionCapacitance & Deep DepletionMOS Charge ConditionsFrequency Dependence of CapacitanceSurface-Channel MOS Junction & Potential WellsDeep Depletion EquationsCharge-Coupled Devices (CCDs)CCD Concept3-Phase CCD OperationCharge Transfer in CCDsCCD Imaging SystemCCD Device Layout3-Phase CCD OperationDifferent CCD Layouts & Clocking SchemesOverlapping Gate CCD StructureChannel Confinement TechniquesBuilt-In WellsBuried Channel CCD (BCCD)BCCD Band DiagramsCCD ArchitecturesColor Capture MethodsSemiconductor-Insulator-Semiconductor EFEVECEF EV EC EFEVECEF EV EC EFEVECEF EV EC EI EI EI EI EI EI qV2 qV1 Depletion Surface becomes “less n-type” Accumulation Surface becomes “more n-type”, Inversion: Surface becomes p-type (p>>n) n n Accumulation Positive voltage V1 applied Positive voltage V2>V1 appliedmϕ=Metal Work Function: Potential required to extract an electron from the metal to vacuum χ= Electron Afinity: Potential required to extract an electron from the conduction band of a semiconductor to the vacuum. ++−=BgmmsqEψχφϕ2: Work Function difference=difference in Fermi levels prior to contact. Metal-Oxide-SemiconductorEF Bqψ EC EI EF EV Vacuum Level χq 2/gEmqϕmsqϕMetal Semiconductor χq2/gEBqψ EC EI EF EV mqϕmsqϕEMetal Semiconductor Oxide -Q+Q Vacuum LevelReal Al/SiO2/p-Si Junction 31510*2−= cmNADifference in Work Functions of the metal and the semiconductor leads to energy-band bending and space-charge regions. The flat-band voltage FBVis the voltage needed on the metallic terminal (gate) to cancel the original Fermi level difference. So in flat-band condition, msFBGVVϕ== For an ideal MOS structure, FBmsV==0ϕ Ideal MOS JunctionEnergy-Band Diagram For Ideal MOS JunctionsSurface Potential ()qxEExII/)()()( −+∞=ψ: Energy band bending at point x ()sIIqEEψψ=−+∞= /)0()()0(: Surface potential (total bending between surface and bulk). 0<sψ Accumulation of holes (band bends upward) 0=sψ Flat Band Condition Bsψψ<<0 Depletion of holes, creation of space-charge-region (band bends downward) 0=sψ Midgap with issnpn== and IFEE= at the surface BsBψψψ2<< Weak Inversion bulksipnn<< sBψψ<2 Strong Inversion bulkspn >Total Charge in Semiconductor ()qxEExII/)()()( −+∞≡ψ: Energy Band bending at point x −=TppVExppxpψ0)( =TppVExpnxnψ0)( sxdxdερψ)(22−= (Poisson’s Equation) ()pApnNpqx −−=)(ρ −−−−−= 1][1][0022TpTpsVExpnVExppqdxdψψεψsssurfacesurfaceQdxdEεψ−=−= Solving (Sze 7.2.1) leads to:Voltage Drop Across MOS Junction Gate Voltage sigVVψ+= (Ideal MOS junction) FBsigVVV ++=ψ (Non-Ideal MOS junction) sψis due to space charge near, and at the semiconductor surface dEVii=is due to the electric field in the insulator sssQE =εwhere sQis the total charge in the semiconductor iissEEεε=where sEis the electric field at the semiconductor surface Everything can be calculated as a function of sψor Vg Threshold Definition (p-type semiconductor) The threshold voltage thVis reached when the concentration of electrons at the surface is equal to the original holes concentration: appNpsurfacen≈=0)( At threshold, an inversion layer of electrons on the surface of the semiconductor appears.Charge, Field and Potential at InversionCapacitance, Deep Depletion The total capacitance is due to the capacitance the inversion layer (iC) and the depletion/inversion layer capacitance (DC) in series dCii/ε=Oxide capacitance=parallel plate capacitor DiDiCCCCC+= At high frequency, the inversion layer cannot be generated. All the charge in the semiconductor is in the depletion layer (deep depletion condition).Frequency Dependence of CapacitanceInversionp-TYPE(a) Low Frequency(b) High Frequency(c) Deep DepletionAccumulation DepletionCiCDVNAdMOS Charge ConditionsSurface-Channel MOS Junction & Potential Wellsp-TYPEDeep Depletion EquationsNo Signal/Empty WellSignal Present/Occupied WellAssqN WEε=()sig AssQqNWEε+=Surface Field()sig AiiQqNWEε+=GFBsigAsiiVVQqN WCC−=++ΨOxide FieldGFBi sAsiVV VqN WC−=+Ψ=+ΨGate Voltage22AssqN WεΨ=12GFBsigssAsiiVVQqNCCε−=+Ψ+ Ψ22AssqN WεΨ=12GFBssAsiVVqNCε−=Ψ+ΨSurface PotentialAiiqN WEε=Gate Voltage/Surface PotentialRelationshipCCD Concept3-Phase CCD OperationCharge Transfer in CCDsCCD Device LayoutDifferent CCD Layouts & Clocking SchemesOverlapping Gate CCD Structure• Want to improve coupling between wells• Control the electrode separation• Easier to overlap gatesChannel Confinement Techniques• Keep charge confined in lateral directionBuilt-In Wells• Charges lost in transfer process• Surface states can trap charges at Si-SiO2interface• Solution: move charge away from surfaceBuried Channel CCD (BCCD)• Avoid interaction of signal charge with surface and interface states• Shift charge storage and transfer towards bulk semiconductorBCCD Band Diagrams2222220 0 0 DnsAnnpsddxdxqNdxxdxqNdxxxxdxεεΨ=−<<Ψ=− < <Ψ=<<+Poisson Equations for PotentialCCD Architectures• Linear array with shift register• 2D array (full-frame imager)• 2D array with storage (frame-transfer)• Alternating line arrays and read-out registers (interline)Color Capture Methods• CCDs inherently monochrome so it takes effort to get color¾ Take 3 exposures with different optical filters¾ Optics to split image into 3 parts output to color filter and CCD¾ CCD with on-chip filters for each