1Low-Power, Radiation-Tolerant Reconfigurable Computing Platform for SpaceGregory W. Donohoe, PhD, PEECE/CAMBRUniversity of IdahoMoscow, ID [email protected] Pen-Shu Yeh, PhDNASA/GSFCCode [email protected] computingChallenge problemInterconnect strategyLow-voltage signalingSignal integrityClock & data recoveryConclusion3Research TeamDr. Gregory W. Donohoe, CAMBR/UIdaho, PIDr. Pen-Shu Yeh, NASA GSFC, Code 567, NASA LeadRick Lyon, NASA GSFC, Space ScientistJoe Hass, CAMBR/UIdaho, VLSI LeadDr. David Buehler, CAMBR/UIdaho, Software LeadResearch AssistantsVictor Cordero-Calle, John Geidl, Yichao Ye -- ApplicationsTu Le --Verification & ApplicationsChris Canine, Bill Walker – VHDL, VerificationSenior Design TeamCameron Dennis, Chris Canine, Aseer ItyavvarFaculty CollaboratorsProf. Bob Rinker (Computer Science) – Advanced softwareCS Grad Students: Andrew McConaghy, Paul NathanGSFC Engineer: David Fisher, Printed Circuit Board & System Design4Objectives1. High computation throughput3.2 Giga Multiply-Accumulates/sec2. Low power consumption160 Mega Multiply-Accumulates/watt3. Radiation tolerantBuilt on CAMBR Rad-hard by design technologyStrategy:1. Put the power where it counts• Large-scale data path parallelism• Minimize control overhead: instruction fetch, memory access2. Low-power, radiation-tolerant chips3. Low-voltage board-level signaling4. Energy management5Mission ApplicationsPlanet Surface RoversHigh-speed, on-board sensing (vision, tactile, laser). Feature extraction for object recognition, navigation. Low power extends batter range, operation in the dark.Magnetosphere Multi-Scale (MMS) InstrumentSmall spacecraft to study solar wind/burst impact on magnetosphereSignal processing, feature extractionDeep Space ExplorationOn-board radar signal processingHyperspectral instrumentsImage conditioning, flat-fielding before compressionLevel-1 radiometric correction, solar irradiance normalizationPhased-array telescopesPractical alternative to large telescope lensesRequires intensive processing for phase estimationManned Repair MissionsMachine vision, image processing for inspection and repair6Platform ElementsProcessor Node: Field Programmable Processor ArrayMemory: Reconfigurable Memory ModulesInterconnect: Reconfigurable Crosspoint NetworkControl: ColdFire MicrocontrollerHost Interface InterconnectProcessor NodeProcessor NodeProcessor NodeProcessor NodeMemory Memory Memory MemoryInterconnect InterconnectControl7Synchronous Dataflow Computational ModelIOP1PE4PE0PE3PE2PE1FirePE0FireIOP0FireIOP1IOP0FirePE1FirePE2FirePE3FirePE3InputOutputConfiguration phase: set up a pipeline1. Configure PEs, IOs, and interconnects2. Load execution programExecution phase: run a pipeline1. Fire executable modules at appropriate times2. Execute hardware loops3. Terminate on internal or external events8Compare Existing Technology1. Sequential Processors, including Digital Signal Processors• Throughput limited by sequential operation• Excessive power consumption due to complex memory access and control2. Field Programmable Gate ArraysExcessive power consumption due to fine granularity, complex interconnect structureVery difficult to radiation-hardenExample: compute cosine function with six termsIntel 8xC196 16-bit Microcontroller at 50 MHZ31 Instructions4.096 microseconds/sample, 201.7 Kilosamples/secReconfigurable Platform at 50 MHz20 ns per sample, 50 MSamples/secExample: JPL Radar Signal Processor with 20 Xilinx Virtex FPGAs400 Watts, no radiation tolerance1200 Watts with Triple Module RedundancyEstimate four Field Programmable Processor Array chipsRadiation tolerant, 20 Watts9Challenge Problem boomtelescopes80 cm 40 cm Space-based phased-array telescope• Three telescopes on flexible boom• Controllable in three axes: tip, tilt, and piston• Processing requirements1. Estimate wavefront tip, tilt from images2. Estimate piston displacement from interferogram3. Formulate feedback control matrix4. Update tip, tilt & piston at 800 Hzoptic axiszxytilttip120μmoptic axiszxytilttip120μmSolar Viewing Interferometry Prototype (SVIP)10Tip & Tilt1232DFour images:Telescopes 1, 2 and 3Telescope 2 buffered ¼ secondCorrelate 3 images pairs• Estimate horizontal & vertical displacement• Sub-pixel accuracy required• Simple geometric calculation to compute tip & tiltCorr(1,2)Corr(2,3)Corr(2,2D)Image 2 buffered (delayed) ¼ sec11Spatial CorrelationCorrelation can be performed in spatial or frequency domainSpatial domain more appropriate for dataflow architecture()∑∑−=−=++−++=101022121),(),(),(minjjyixIjyixIIIdiffUse distance metric:Produces smooth error surface for accurate sub-pixel peak detection peak12PistonPupilBD12θyPSFθxλ+Piston => Aperture 1 Leads-Piston => Aperture 1 LagsFocussingLens 1Pupil ImagesCCD 1Dispersion1024128GratingCollimatingLens 12FromBeamCombiner0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.850.00.51.01.52.02.53.0Wavelength ( μm)Point Response Function•In λ-space gives chirp• In k-space gives single f• phase shift gives lead/lag13Piston CalculationEstimate this angleα = 0: no piston displacement errorα > 0: aperture lagsα < 0: aperture leadsαInterference patternxyMethod: Interference pattern = f(x,y)Average α over central region of imageEstimate df/dx and df/dy by convolving with edge operators xf∂∂/⎥⎥⎥⎦⎤⎢⎢⎢⎣⎡−−−101101101⎥⎥⎥⎦⎤⎢⎢⎢⎣⎡−−−111000111VerticalHorizonalα=tan-1(vert/hor)14Field Programmable Processor ArraySuite of support software• Application development, compiler, simulator, run-time.• Integrated with existing software platforms.A reconfigurable, embedded data processor VLSI chip for spacecraft• Targeted to rad-tolerant, 0.25μ CMOS process• Implements a reconfigurable, synchronous data pipeline• Run-time reconfigurable• Off-loads data intensive, streaming tasks from host• Can be tiled to handle large-scale problemsA low power, radiation-tolerant alternative to FPGAs for reconfigurable computing.15Data MemoryAddressDataRAMControlBasic element: Random Access Memory• Model as an array: address = index• Application supplies addresses and control signalsProblem:• Address generation consumes processor resources and instruction cycles• Address lines consume routing resources and power FPPA is a shallow memory architectureOn-board data memory limited to registers• Difficult to build large memory on a logic process• Amount