COLUMBIA UNIVERSITY SCHOOL OF ENGINEERING AND APPLIED SCIENCE EHDL Easy Hardware Description Language COMS W4115 Programming Languages and Translators Project Proposal Paolo Mantovani pm2613 Mashooq Muhaimen mm3858 Neil Deshpande nad2135 Kaushik Kaul kk2746 September 28 2011 1 Motivation Fueled by advances in integrated circuits technology hardware systems have grown increasingly complex over the past several decades This rise in complexity makes the hardware designer s job difficult Our work aims to alleviate some of the difficulty by introducing an HDL Hardware Description Language that is easy to learn and code in We feel that traditional HDLs such as VHDL are unnecessarily verbose and more lowlevel than they need to be By developing a language that is succinct and at the same time defers more implementation details to the compiler we hope to increase the productivity of hardware designers 2 Language Overview We propose a language with a C like syntax The user of our language is assumed to have rudimentary knowledge of digital logic Experience with an imperative programming language such as C will also be beneficial We call our language EHDL Easy Hardware Description Language The EHDL compiler will translate the EHDL code to VHDL Each EHDL statement will be translated into a combinational block Functions will be mapped to components entity and architecture signals list component declaration and instantiation The compiler will automatically add to the logic component the inputs clock and reset along with an output valid flag The output valid flag will be used to indicate if the output values are valid stable The flag will always equal 1 when the function describes a combinational block the synthesizer will remove the clock reset and the valid flag in this case In the case of a multi cycle unit the user can read the flag to handle the handshake between logic components if function name valid EHDL functions will be able to return more than one value A novel feature of our language will be a special keyword POS that gives the user the ability to place positive edge triggered registers that break the combinational path This can be used to pipeline speed up the design Re timing will require only moving the POS statement within the code without having to rewrite any of the functional blocks Our language will handle loops If the same variable is modified in every loop cycle a register will be automatically inferred to allow feedback in the circuit Due to the fact that a synthesizable register must have a constant reset value when the arguments of a function are used as loop variables see the gcd example is Section 4 the input sensing of the associated logic block will be turned off until the loop finishes its execution Once the loop is done executing i e the loop condition ceases to hold the output valid flag will be used to indicate that the output ports now contain valid values At the next clock cycle the loop will restart and load the new input values Our language will also support VHDL like for generate loops 3 Keywords EHDL will include the following keywords this list is not exhaustive CLOCK period identifier is the key word to create a clock signal RESET SYNC clock HI LO identifier or RESET ASYNC HI LO identifier are the key words to create a reset signal POS clock reset enable generates a register for each temporary variable introduced after the previous keyword POS or from the beginning of a logic block function After applying POS the identifiers 2 for variables will not change however the old variables inputs of the registers will not be accessible An exception can be introduced to manage the situation of an asynchronous control signal such as clock enable In this case the variable must be declared as ASYNC INPUT identifier testbench input pattern defines an input for the top entity and can be used to generate the testbench OUTPUT identifier testbench input pattern defines an output for the top entity and can be used to generate the testbench TOP identifier blocks list defines the top entity of the design The block list can contain simple expressions combinational logic variables declarations internal signals POS registers function call components instantiation Common logic and arithmetic operators 4 Example This example illustrates how a classic algorithm for computing the greatest common divider GCD will be implemented in our language Figure 1 shows the algorithm written in the high level programming language C so that the reader may become familiar with the algorithm Figure 2 shows the EHDL code for the GCD algorithm Appendix A shows the same algorithm implemented in VHDL this is the version we intend to produce with our compiler when it gets the EHDL code as input A cursory inspection of Figure 2 and Appendix A should convince the reader of the ease and conciseness of our proposed language int gcd int a int b while a b if a b a b else b a return a Figure 1 An implementation of the GCD algorithm in C 1 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 CLOCK 100 ns clk RESET ASYNC rst INPUT int a 37 int b 55 OUTPUT int c int gcd int a int b while a b if a b a a b else b b a return b TOP gcd wrap inputs and outputs are already declared c gcd a b POS clk rst gcd valid return assignment of the main output c is seen at the output of a register Figure 2 An implementation of the GCD algorithm in EHDL 3 5 References 1 Edwards Stephen COMS W4115 Programming Languages and Translators Lecture Retrieved on September 27 2011 from http www cs columbia edu sedwards classes 2011 w4115 fall ocaml pdf 6 Appendix A An implementation of the GCD algorithm in VHDL library ieee use ieee std logic 1164 all use ieee std logic signed all entity gcd is port clk rst gcd a gcd b gcd out gcd valid in std logic in std logic in std logic vector 31 downto 0 in std logic vector 31 downto 0 out std logic vector 31 downto 0 out std logic end gcd architecture beh of gcd is Combinational logic output signals signal while l7 if l8 std logic signal sub l8 sub l9 std logic vector 31 downto 0 Automatically generated registers signal a reg b reg std logic vector 31 downto 0 Automatically generated internal input signals signal a std logic vector 31 downto 0 signal b std logic vector 31 downto 0 Automatically generated internal output signals signal gcd out int std logic vector 31 downto 0 signal gcd valid int std logic begin beh input signals assignment a gcd a b gcd b Automatically generated
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