David W. Parent EE Department Phone 408.924.3963 1 Washington Sq SJSU San Jose CA, 95192 Fax 408.924.3963 Documentation for Spartan Semiconductor Services NMOS Mask Set.Chapter 1 Documentation for NMOS Mask Set Top View In Figure 1, we see the legend use for this mask set. Mask 1 consists of GDS layer 1 XORED with GDS layer 49 and the digitized data is clear. This means all non-common areas between GDS 1 and 49 will have an open widow and light from the aligner is allowed through these areas. All other areas of the mask will be chrome. Mask 1 is the N+ Source/Drain/Resistor step. Mask 2 consists of GDS layer 2 XORED with GDS layer 49. The digitized data is clear is the same manner as Mask 1. This is the gate etch step. This step also “Pre-Etches” the contact step. Mask 2 is aligned to Mask 1. Mask 3 consists of GDS layer 3 XORED with GDS layer 49. The digitized data is clear is the same manner as Mask 1. This is the contact etch step and is aligned to Mask 1. Mask4 consists of GDS layer 4 only and the data is digitized dark. This means that wherever layer 4 is drawn will be chrome on the mask and block light from passing through the mask. Mask 4 is aligned to Mask 3.2 • Figure 1: Legend3In Figure 2, we see the complete view of all layers of the mask set over the whole 4” wafer. The three process widows are in the top third of the wafer and are labeled as S/D, GATE, and CONT. Note that the CONT window will be “pre-etched” during the GATE step (Mask 2) so after mask two there will be all three process widows will be visible. The alignment marks can be seen at the extremes of the horizontal axis of the wafer (The areas inside the purple regions.). There are addition alignment marks along the centerline as well for processing smaller diameter wafers. The four big squares in the alignment marks are just to help the operator to find the much smaller alignment marks set in-between them. There are also seven sets of PL test structures (The red yellow and blue features.). The blue squares are 40 pin test structures. There are six different test structures. The first is the Material test structure, which appears almost all blue with a little bit of green. The second is the DEVICE1 block, which has transistors and diodes and BJTs. The third is the DEVICE2 block and contains transistors with a gate length of 16 microns arranged to examine orientation effects. The forth is the DEVICE3 block which contains transistors with a minimum gate lenth of 32 microns to examine orientation effects. The fifth block the DEVICE4 block, which contains transistor witth the source and body shorted, and the gate and drain shorted. The gate lengths vary from 6 microns to 14 and are arranged to look at orientation effects as well. The LOGIC block consists of inverters, nand gates and ring oscillators. The blocks are laid out in rows from left to right in this order: MATERIAL, DEVICE1, DEVICE2, DEVICE3, DEVICE4 followed by LOGIC. Each column consists of one type of test block. It should be very easy to divide the testing to row and column addresses. The blocks are clearly labeled. • Figure 2: Complete View of all layers of the complete 4” wafer.4Alignment Marks In Figure 3, we see the top view of the alignment marks. The four big squares which appear orange (due to the fact that all the layers are have these large squares and the colors bleed through.). The alignment marks that will be used are in the center of the cross formed by the four squares. The four squares will be chrome and surrounded by a clear region are used to help set up the mask set for alignment. • Figure 3: Top view of alignment marks.5In Figure 4, we see the conventional alignment marks to be used. Mask two should be aligned using the marks with two sets of squares in squares and checkerboard. Mask three uses the row that has three sets of squares in squares and checkerboards. Mask 4 uses the row with four of these features. For convenience, which row to line up to will be printed on the wafer. In addition, the alignment marks for a given mask are spaced differently so that it should be impossible to align to the wrong layer. • Figure 4: Conventional Alignment marks.6 PL Test Structures In Figure 5, we see all the test structures use to check alignment, and registration of the PL process. • Figure 5: Top view of the PL test structures.7In Figure 6, we can see the LBAR test structures to check how well the PL process can replicate long features, and corners. The structures are 3, 4, and 8 microns wide. • Figure 6: LBAR PL test structures.8In Figure 7, we see the test features for the proximity effect. The proximity effect can be seen as a narrowing of the middle line sandwiched between the two squares. This set contains 3 micron featrues and four micron features. • Figure 7: Test Structure for Proximity Effect.9In Figure 8, we see structures for contact like structures. Even though these features appear in every layer, they are only really important for the contact layer(Mask 3). In addition, since the contacts for our devices are 16 microns across, these test features are too small to optimize our λ=8µm process. It should also be noted that one can not optimize the CONTACT PL and the LBAR PL at the same time. The features are there so that a comparison can be made between contacts form with optimized and non-optimized conditions. One should also compare the contacts formed in the center of the mass of contacts and the insolated contacts. This set contains features of 3, 4, and 8 microns. • Figure 8: Contact Test Structure.10 In Figure 9, we see a standard needle structure used for measuring how close two objects can be placed. The needle will disappear if the PL process is not working for a particular separation. The needles start at 7 microns separation and progress down wards from 6, 5, 4, and 3 microns. • Figure 9: Needle Test Structure for Registration.11In Figure 10, we see a test structure used to monitor how well the metal lines are able to go over steps in oxide thickness. The structures are the same width a the LBAR cell. • Figure 10: Step Coverage Test Structure.12In Figure 11, we see test structures use to measure the resolution of the PL process. As long as the 8-micron features are present and not washed out the devices will work. On Mask 1 it would be best if at least the 6 microns features came our properly, other wise the