I’ Quantum Mechanical Aspects of Transport in Nanoelectronics GREGORY L. TIMP AND RICHARD E. HOWARD, MEMBER, IEEE Innovations in semiconductor technology have provided us with an opportunity to examine devices with vertical and lateral di- mensions less than 100 nm-comparable to the wavelength of the electron at the Fermi energy. At low temperature, the confinement and the coherence of the electronic motion on the scale of the electron wavelength give rise to gross deviations from classical charge transport that describes the resistance found in large conventional devices. For example, the low temperature electrical resistance of a high mobility, semiconducting wire 100-nm wide, IO-nm thick, and 200-nm long is nonlinear; it does not scale with length; it can be quantized as a function of the width and charge, it depends on the configuration used to measure it; and it is nonlocal, i.e., the current at one point in the wire depends not only on the electric field at that point, but on electric fields micrometers away. These peculiarities are due to the wave nature of the electron. In this paper we discuss some of the implications quantum mechanics has on the performance of nanometer-scale devices. I. INTRODUCTION In pursuit of higher density and faster integrated circuits, the physical dimensions of individual electronic devices, i.e., metal-oxide-semiconductor field effect tran- sistors (MOSFET’s) and the interconnections between transistors, have plummeted. For example, in 1958 [1], the first integrated circuit was produced at Texas Instruments. It was made from one transistor, three resistors, and a capacitor and was about 1-cm long and 0.5-cm wide. In 1969, Intel manufactured a random access memory (RAM) with 256 b of memory and about lo3 components using a 12-pm design rule in about the same area. By 1990, Hitachi had announced the prototype of a 64-Mb RAM with about 108 components manufactured with electron beam lithography using a 300-nm design rule in =l cm’. There are alternative ways to improve performance without reducing the dimensions of individual electronic devices. For example, three-dimensional integration [2], [3] has been used to increase density, and special purpose chips have been used to improve the speed of a particular computation like convolution [4]. Despite these alternatives, reducing the physical dimensions of a device in an integrated circuit Manuscript received September 14, 1990. The authors are with AT&T Bell Laboratories, Holmdel, NJ 07733. IEEE Log Number 9101227. still represents the most practical means to improve general performance. The advent of high throughput X-ray [SI-[9], and electron beam lithographies [lo], [11] suggests that this will be the case even beyond 300-nm design rules. Eventually, practical, economical, and physical [ 121 - [ 151 limitations will conspire to arrest the decrease in physical dimensions of devices within an integrated circuit. The diminution of integrated circuits achieved so far has been feasible because of the possibility for compromise within the design rules for an MOS circuit between different limi- tations imposed by fabrication, circuit design, performance, and reliability [16]. The problem, that will ultimately check our ability to compromise between fabrication, design, and reliability, can be represented succinctly as follows: We do not yet possess a transparent, analytical solution of the equations that describe how a MOSFET works [16]-[18]. The equations that describe the operation of a MOSFET are Poisson’s equation, and the constitutive and continuity equations for the current density. These equations treat the MOSFET from a classical perspective; i.e., the charge carriers are treated like billiard balls, and averages over the velocities are used to predict the transport coefficients. So far, the principle of scaling [19], [20] the equations governing the operation of a MOSFET has provided a guide for the accommodation of reduced design rules within existing designs. For example, if the electric field is supposed to be constant, then scaling down the size of a MOSFET means a proportional reduction of the horizontal and vertical device dimensions, lithography patterns, and the supply voltage [19]-[22]. Scaling is not always successful, however [23] -[28]. There are at least three lengths that infringe on the scaling of a MOSFET to a channel length [29], [30] of L,ff = 100 nm or less: 1) the oxide thickness, toz: 2) the junction depth, rJ: and 3) the depletion width, WD. Short channel effects are minimized if the oxide is thin, the junction depth is shallow, and the depletion width is small. For example, electrostatic scaling, where the supply voltage, V~D, is per- mitted to scale differently than the lateral dimensions, sug- gests that to, = 3 nm. r3 = 30 nm. and WD = 35 nm, if 0018-921919110800-1188$01.00 0 1991 IEEE 1188 PROCEEDINGS OF THE IEEE, VOL. 79, NO. 8, AUGUST 1991Leff = 100 nm [25]. In practice, however, a to, = 3 nrri is used either to prevent dielectric breakdown (with electric fields F FZ lo7 V/cm) or tunneling. With a refractory gate material like MO or W or boron-doped poly-Si, tunneling can be precluded only as long as to, 2 4 nm and VD~ 5 1 V, and even then the reliability of the oxide is dubious because of hot carrier effects [31]. Furthermore, a junction depth greater than 30 nm will probably be used to avoid large parasitic resistances [32], (331. Finally, the doping dependence is measured by the depletion width in as much as W, is proportional to the Debye length. The substrate doping is usually chosen to prevent bulk punchthrough (i.e., an overlap between source and drain depletion regions), but there is an upper limit to acceptor dopant concentration at n, = 2 x lo1’ cm-3 that is determined by the dielectric breakdown of the oxide. At a higher concentration, a breakdown voltage on an oxide 4-nm thick cannot invert the Si-Si02 interface. At this concentration, the effect of a statistical fluctuations in the impurity concentration will effect the threshold of a MOSFET made with 100-nm design rules and so affect yield. Beyond scaling, it is necessary to resort to experimental and numerical analysis to