FUNCTIONAL BLOCK DIAGRAMTRUTH TABLEDQH-LevelMAGNETIC FIELD RATINGTest ConditionsELECTRICAL SPECIFICATIONSSymbolStresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect deviceVoltage referenced to GNDRAM power dissipation due to IDDS, IDDOP, and IDDSEI, plus RAM output driver power dissipation due to external loading must not exceed this specificationClass 2 electrostatic discharge (ESD) input protection voltage per MIL-STD-883, Method 3015Maximum soldering temp of 225(C can be maintained for no more than 5 seconds.CAPACITANCE (1)LimitsUnitsRISE/FALL TIMESUnitsDATA ENDURANCEUnitsDATA RETENTIONUnitsREAD CYCLEWRITE CYCLENON-DELAYEDDELAYEDPOWER UP TIMINGPOWER DOWN TIMINGQUALITY AND RADIATION HARDNESS ASSURANCESCREENING LEVELSRELIABILITYPACKAGE OUTLINEORDERING INFORMATION (1)HMXNV0100 www.honeywell.com/aerospace h HXNV0100 64K x 16 Non-Volatile Magnetic RAM Advanced Information The 64K x 16 radiation hardened low power nonvolatile Magnetic RAM (MRAM) is a high performance 65,536 word x 16-bit magnetic random access memory with industry-standard functionality. The MRAM is designed for very high reliability. Redundant write control lines, error correction coding and low-voltage write protection ensure the correct operation of the memory and that it is protected from inadvertent writes. Integrated Power Up and Power Down circuitry controls the condition of the device during power transitions. It is fabricated with Honeywell’s radiation hardened Silicon On Insulator (SOI) technology, and is designed for use in low-voltage systems operating in radiation environments. The MRAM operates over the full military temperature range and is operated with 3.3 ± 0.3V and 1.8 ± 0.15 V power supplies. FEATURES  Read Cycle Time ≤60 ns  Write Cycle Time ≤100ns  Typical Operating Power ≤500 mW Unlimited Read/Write (>1E15 Cycles)  >10 years Power-Off Data Retention  Synchronous Operation  Single-Bit Error Detection & Correction (ECC)  Fabricated on S150 Silicon On Insulator (SOI) CMOS Underlayer Technology  150 nm Process (Leff = 130 nm)  Total Dose Hardness ≥ 3x105 rad (SiO2)  Dose Rate Upset Hardness ≥ 1x1010 rad(Si)/s  Dose Rate Survivability ≥1x1012 rad(Si)/s  Soft Error Rate ≤1x10-10 upsets/bit-day  Neutron Hardness ≥1x1013 cm-2  No Latchup  Dual Power Supplies • 1.8 V ± 0.15V, 3.3 V ±0.3V • 3.3V CMOS Compatible I/O Operating Range is -55°C to +125°C  Package: 64 Lead Shielded ceramic Quad Flat PackHMXNV0100 FUNCTIONAL BLOCK DIAGRAM Memory Array65,536 x 16Column DecoderData Input/OutputRead CircuitsBit Line Current DriversDigit Line CurrentDriversA(7:15)WENWIDQ(0:15)ECC Array65,536 x 5ECC LogicDQCCSDQCOEWE_ASA(0:6)DQCECC_DISABLEERROR SIGNAL DESCRIPTION Signal Definition A(0:6) Column Select Address Input. Signals which select a column within the memory array. A–(7:15) Row Select Address Input. Signals which select a row within the memory array. DQ(0:15) Data Input/Output Signals. Bi-directional data pins which serve as data outputs during a read operation and as data inputs during a write operation. CS Chip select. The rising edge of CS will clock in the address and WE signals WE Write Enable. This signal is latched to enable a write. WE_AS Write Enable Asynchronous – This signal can be used to delay the beginning of the write cycle OE Output Enable. NWI_0 NWI_1 Not Write Inhibit – When set low, these signals inhibit writes to the memory. A high level allows the memory to be written. NWI(0) controls address locations A(15:0) = 0x0000 to 0x7FFF. NWI(1) controls address locations A(15:0) = 0x1000 to 0xFFFF. ECC_Disable Error Correction Disable – Disables the error correction function. ERROR ECC Error flag Test_1 Test_2 These signals are for Honeywell test purposes only. These should be grounded in normal operation. VDD1 DC Power Source Input: 1.8V VDD2 DC Power Source Input: 3.3V 2 www.honeywell.comHMXNV0100 TRUTH TABLE NWI WE & WE_ASY OE MODE DQ L X L Deselected High Z H L L Disabled High Z H L H Read Data Out H H X Write Data In X: VI = VIH or VIL PACKAGE PINOUT 64 GND 63 DQ(2) 62 DQ(3) 61 DQ(4) 60 DQ(5) 59 DQ(6) 58 DQ(7) 57 VDD2 56 GND 55 ADDR(0) 54 ADDR(1) 53 ADDR(2) 52 ADDR(3) 51 ADDR(4) 50 ADDR(5) 49 VDD1 48 GND 47 VDD2 46 ADR(6) 45 ADR(15) 44 WE 43 WE_ASY 42 OE 41 VDD2 40 VDD1 39 GND 38 ADDR(14) 37 ADDR(13) 36 ADDR(12) 35 ADDR(11) 34 GND 33 VDD1 VDD1 1GND 2DQ(1) 3DQ(0) 4CS 5NWI(0) 6VDD2 7VDD1 8GND 9NWI(1) 10ECCDISABLE 11ERROR 12DQ(8) 13DQ(9) 14VDD2 15GND 16HMXNV1000VDD1 17DQ(10) 18DQ(11) 19DQ(12) 20DQ(13) 21DQ(14) 22DQ(15) 23GND 24VDD2 25ADDR(7) 26ADDR(8) 27ADDR(9) 28ADDR(10) 29TEST 30TEST 31GND 32RAM and ROM Functional Capability This MRAM incorporates two write control signals allowing the two sections of the memory to be controlled independently. The two NOT WRITE INHIBIT signals, NWI(0) and NWI(1), allow one section of the devices to operate as a RAM and the other to operate as a ROM at the full control of the user. 3 www.honeywell.comHMXNV0100 SOI AND MAGNETIC MEMORY TECHNOLOGY Honeywell’s S150 Silicon On Insulator (SOI) is radiation hardened through the use of advanced and proprietary design, layout and process hardening techniques. The 150 nm process is a technology with a 32Å gate oxide for 1.8 V transistors and 70Å gate oxide for 3.3 V transistors. The memory element is a magnetic tunnel junction (MTJ) that is composed of a magnetic storage layer structure and a magnetic pinned layer structure separated by an insulating tunnel barrier interlayer. During a write cycle, the storage layer is written by the application of two orthogonal currents of the desired polarity using row-and-column addressing. The resistance of the MTJ depends on the magnetic state of the storage layer, which uses the pinned layer structure as a reference, and which enables sensing, signal amplification, and readback. The resistance change is a consequence of the change in tunneling magnetoresistance (TMR) between the storage and pinned layers that depends on