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Brown EN 164 - Computer System Design Lecture 5: Instruction Sets

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1Computer System DesignLecture 5: Instruction SetsProf. R. Iris BaharEN164February 5, 2007Reading: Appendix B, section B.1-B.6 EN164Lecture 4-2Lab 1 Information• Lab 1 handouts are now available• Labs are due (i.e., need to be checked off by a TA by Thursday, February 15, by 10pm• Lab write ups are due Friday, February 16, by 5pm• TAs will have their lab hours posted on the web by tomorrow• Lab is in room 196–The lab is normally locked; coordinate with TA hours to access the labEN164Lecture 4-4Accessing Internal Storage• How should memory be accessed?– Directly or through registers?• How should ALU operations be expressed?– Implicit or explicit operands? – compact or flexible?• Example: How should we represent C = A + B ?Stack Accumulator Reg (reg-mem) Reg (load-store)Push A Load A Load R1, A Load R1, APush B Add B Add R3, R1, B Load R2, BAdd Store C Store R3, C Add R3, R1, R2Pop C Store R3, C• Registers: fast, exploit locality, reduced memory traffic, easier to re-orderEN164Lecture 4-5Register ArchitecturesVAXVariation in instr size (hard to decode), frequent memory accesses, variable instr latencyMost compact code size, doesn’t waste registersMemory-Memory (2 mem, 2 ops) or (3, 3)Intel 80x86, Motorola 68000One of the operands is destroyed, instrlatency is variableCan access data without doing a load, small code sizeRegister-Memory (1 mem, 2 ops)Alpha, MIPS, ARM, PowerPC, SPARCHigh instr count and code sizeSimple, fixed-length, simple code-generation, easy pipelining and parallelism extractionRegister-Register(0 mem, 3 ops)ExamplesDisadvantagesAdvantagesTypeRISCCISCCISCEN164Lecture 4-6RISC vs. CISC ISAs• Reduced Instruction Set Computer (RISC): by using a few simple instruction primitives, the hardware is simpler–easy to extract parallelism– easy to effect high clock speeds• Complex Instruction Set Computer (CISC): if you do it in hardware, it’s fast Æ therefore, implement every functionality in hardware–Rich instruction set– Complex decoding– Complex analysis to identify dependences– Danger is a slower cycle time and/or a higher CPI– Goal is to reduce number of instruction executed• Why is this important??EN164Lecture 4-7Characteristics of RISC ISAs• Common characteristics of all RISCs–Single cycle issue– Small number of fixed length instruction formats– Load/store architecture– Large number of registers• Additional characteristics of most RISCs–Small number of instructions in the instruction set– Small number of addressing modes– Fast control unit• Virtually all new instruction sets since 1982 have been RISC based2EN164Lecture 4-8Example Instruction Sets• MIPS –Popular example of a RISC instruction set– Relatively easy to learn and use• X86–CISC instruction set developed at Intel (1stversion in 1978)– Why is it still popular today, despite the trend to RISC?– How is Intel able to incorporate RISC characteristics into its processor design while still implementing the X86 ISA?EN164Lecture 4-9Addressing Modes for MemoryRegs[R1]ÅReg[R1]+Mem[Regs[R2]]Regs[R2]ÅRegs[R2]+dAdd R1,(R2)+AutoincrementRegs[R3]ÅRegs[R3]+Mem[Regs[R1]+Regs[R2]]Add R3, (R1+R2)IndexedRegs[R1] Å Regs[R1] + Mem[Mem[Regs[R3]]]Add R1, @(R3)Memory indirectRegs[R1] Å Regs[R1] + Mem[1001]Add R1,(1001)Direct/absoluteRegs[R4] Å Regs[R4] + Mem[Regs[R1]]Add R4, (R1)Register indirectRegs[R4] Å Regs[R4] + Mem[100+Regs[R1]]Add R4, 100(R1)DisplacementRegs[R4] Å Regs[R4] + 3Add R4, #3ImmediateRegs[R4] Å Regs[R4] + Regs[R3]Add R4, R3RegisterMeaningExampleAddressing mode• More addressing modes Æ lower instruction counts, more complexity • Most common modes: immediate and displacement– How do you simulate register indirect and direct addressing with displacement addressing mode?– Which would you more likely find in a CISC-like

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