1Computer System DesignLecture 8: Pipeline HazardsProf. R. Iris BaharEN164February 12, 2007Reading: Appendix A, sections A.1-A.3 EN164Lecture 8-2Pipelining• What makes it easy (specifically for implementing RISC)–all instructions are the same length– just a few instruction formats– memory operands appear only in loads and stores– aligned data: one memory access for one data item• Hazards make it hard–next instruction cannot execute in the following clock cycle– structural, control and data hazards• What makes it really hard–exception handling– trying to improve performance with out-of-order execution, etc.EN164Lecture 8-4Instruction Steps in Detailwhat kind of branch instructions are processed by this pipeline?EN164Lecture 8-5Pipelined Datapath• Reuse of functional units in every clock cycle• Additional hardware– Separation of pipeline stages by pipeline registers• Latching data between stages into registers increases latency per instruction– Multiple functional units if used by several instructions at the same time (for removing structural hazards)• What HW unit is duplicated in our MIPS 5-stage pipeline?• Extended control– Strict “sequentialization” of instruction • every instruction goes through all stages– Check for hazards– Introduce stalls to remove hazardsEN164Lecture 8-7Pipelined DatapathEN164Lecture 8-8Some Potential Hazards• Usually data moves from left to right (conceptually) Data moving from right to left affects later instructions• Write back into the register file can lead to data hazards• Selection of the next value of the PC leads to control hazards• A simple way to deal with hazards it to STALL the pipeline, leading to inefficiencies in throughput2EN164Lecture 8-10Potential Hazards• Structural Hazards:– Resource conflicts where HW cannot support all possible combinations of instructions through the pipeline– Examples: Single memory port, R/W register file in same cycle– How does our 5-stage pipeline deal with these hazards?– What would happen if our pipeline had only 1 memory port?WBMEMEXEDIFstoreWBMEMEXIDIFstallshiftWBMEMEXIDIFsubWBMEMEXIDIFaddWBMEMEXIDIFload10987654321EN164Lecture 8-11Potential Hazards• Data Hazards:–Instruction depends on results of previous instruction not yet availableWhere are the data dependencies in the following code sequence?ADD R1, R2, R3 // R1ÅR2+R3SUB R4, R1, R5AND R6, R1, R7OR R8, R1, R9XOR R10,R1, R11–How does our register file design help avoid data hazards? – Do we always have to wait until the data is written to the register file in order to use results?EN164Lecture 8-15Examples of Data HazardsCC1 CC2 CC3 CC4 CC5 CC6Time (in clock cycles)IM Reg DM RegIM Reg DM RegALUALUIM Reg DM RegIM Re g DM RegALUALUadd r1, r2, r3sub r4, r1, r5and r6, r1, r7or r8, r1, r9How many cycles do we need to stall to handle the data hazards?EN164Lecture 8-16Data Hazards• Stalling to avoid data hazardsMEMEXIDIFXORWBMEMEXIDIFstallstallORWBMEMEXIDstallstallIFANDWBMEMEXstallstallIDIFSUBWBMEMEXIDIFADD10987654321Why do I stall the SUB starting in the ID stage and not the IF stage?Are any stalls strictly necessary