ECE 3235 Electronics IIFrequency response of a CMOS common-source amplifierUpdated on 10/11/121. Objective2. Procedure3. Interested in more amplifiers? (This part is optional)This part is optional.If you are interested, size the width/length ration of the following common-based and source-follower in CMOS transistors, make sure the transistors in saturation region and then simulate the circuit to identify -3dB bandwidth. Compare to the common-source amplifier.ECE 3235 Electronics IIExperiment # 5Frequency response of a CMOS common-sourceamplifierUpdated on 10/11/12Note: you might want to bring calculator to the lab1. ObjectiveThere are two objectives to this experiment. One is to expose you to the very difficultproblem of transistor sizing for analog circuit design (do not worry: we will just have aglimpse of it). In contrast to digital circuit design, transistors in analog circuits typicallyhave a very large range of sizes. Getting the right sizes are very important to circuitoperation. For example, as you know, you need to have correct DC biasing in order tohave transistors work in saturation region. Easy to say, but it is a difficult task. Even inthe case of a single stage amplifier. (This is also one main reason that why analog circuitdesign is so special and analog designers are so precious in the markets). The other objectis to simulate the -3dB bandwidths and compare it to your theoretical calculations.2. ProcedureFigure 1. A Common-Source Single Stage Amplifier in CMOS transistorsThe above Figure 1 shows a common-source single stage amplifier in CMOS transistors.The circuit topology is very similar to the one we discussed in class (Page 500 in thebook). One slight modification is that we replaced the current source with a resistor RD.Note that the three capacitors Cgs, Cgd and Cdb are parasitic capacitors, so please doNOT include them in your schematic design in Cadence. They are simply drawn to1help you identify the parasitic components that affect the frequency response of thecommon source amplifiers. So, the task to conduct frequency response of the circuit inthe follow several stages.1 ) draw the circuit schematic in CadenceHere, we will use an industry commercial CMOS circuit design technology called TSMC(Taiwan Semiconductor Manufacturing Company) 0.25um technology. To do that, typethe following command from a terminal prompt: cp –rf /zpool1/research/thua/ece3235_test/tsmc025pdk ~/cadence/Again, please note from Lab 4, the label “~” stands for the home directory, the directory where you are once you log into the system. For example, suppose your login name is “xxx0033”, then “~” should stand for “/zpool1/usra/ece3235/fall10/xxx0033”. You an type “pwd” in the command window to verify (pwd shows the current directory).After you type in the above command, you should see a directory named tsmc025pdk under ~/cadence. Your model file will be there in the sub-directory models. To build up circuits, you need to include the technology files in the cds.lib file. Now open cds.lib using the text editor (by click documents on the desktop and go to ~/cadence). Add the following line at the end of the file: DEFINE tsmc25rf ~/cadence/tsmc025pdk/tsmc25rfThen close the file.Important note: (1) If you are also in ECE4311 VLSI Design, please do not type the above two commands, since you should already have it in your directory.(2) If you have trouble using UNIX commands, please type the commands under TA’s supervision.(3) After you copy the files, go to ~/cadence directory and start Cadence software by typing virtuoso & at the command prompt. You should see a new library called tsmc25rf when you open Library Manager. If not, please ask help from TA.(4) Now, use what you have learned from Lab 4 to create a new library called lab5 and then create a cell called common-source-amplifier. Make the schematic for the cell as shown in the following figure:2To simplify the amplifier design for you, set Rs=50Ohm and RD=10kOhm. For the input voltage source, put in a VSIN block from analogLib. Please enter its properties including DC voltage and AC magnitude. For example, you can set DC voltage to 0.65V and AC magnitude to 1V. How to set up the NMOS transistor is explained as follows. Since you need a NMOS transistor, you will need to select the symbol of nmos from analogLib. Put in the initial values for the nmos as shown below:3Be sure to set the field of Model name to nch. (5) for the power supply vdd, select vdd from analogLib. Now properly wire up your circuit.4(6) a warning may be issued after you check and save your schematic. Basically, it is saying that the output node does not connect to a load or simply floats. You can neglect it.(7) when you are ready to simulate your circuit, open Analog Design Environment (refer to last lab on how to do that). Compared to the last lab, here we need to make some changes. First, you only need to set up DC and AC analysis, not Transient analysis. Then, properly select the input and output to be plotted so that the window looks like this:Second, set up your model as shown belowMake sure you specify tt in the section field, otherwise there will be an error. (8) we will need to specify the voltage value for the vdd symbol we used in the schematic. To do that, select setupstimuli… from the Analog Design Environment 5(ADE) window, then a new window pops up. Select Global sources for the stimulus type, then another window appears. Set the field as shown below:Be sure to enable it. What we did is to set the voltage vdd in the schematic window to 2.5V. (9) now you are ready to run the simulation. Try that out. You expect to see the output plot like this:6Pause a second to think about what this plot means? If you agree, the gain of the amplifier now is only about 0.58, too small. In case of any simulation error, please check your circuit and ask TA if you need help. Only proceed to the next section after you can run the simulation correctly. 2 ) design the amplifier for -3dB bandwidthIf you run simulation correctly, you should obtain a plot of input and output as a functionof frequency as shown above. However, the gain is so small, which does not represent agood amplifier. Therefore, you will need to re-size the NMOS transistor length and widthso that a large gain can be obtained, say larger than 15. (Hint: the range of width is 0.5uto 100u and that for length is 0.25u to 1.25u. Do not