EE133 HSPICE HANDOUT Jan / 08 / 2004Some useful links:1) http://www.stanford.edu/class/ee133/handouts/general/vnc.pdf(How to set up and run VNC)1) http://www.stanford.edu/class/ee133/handouts/general/hspice_tut.pdf(Detailed tutorial about HSPICE & Mwaves)2) http://www.stanford.edu/class/ee133/spice/HSpice.pdf(How to set up HSPICE in UNIX environment)a) source /usr/class/ee/DOT.cshrcb) hspice filename.hsp > filename.lis (output)hspice filename.hsp >! filename.lisc) mwaves filename3) http://www.stanford.edu/class/ee133/handouts/general/spice_ref.pdf('Quick' Reference Sheet. More than you need in EE133)*** -------------------------------------------------****** A highly Annotated HSPICE input example file ****** http://www.stanford.edu/class/ee214/example.hsp*** -------------------------------------------------***Remember that the first line is a title!* comments are lines that begin with ** all other lines are evaluated.* model statement. this is an example of an include file.include 'level3models'* Or you may also specify the whole path.*.include '/afs/ir/class/ee214/WWW/level3models'* include this to use mwaves on the output!.option post* param statements allow you to define constants, etc..param cload = 1pF* note that beginning a line with +* appends the time to the previous line* (exceptions: comments cannot continue with +).param rout = 10k+ vdd = 3V+ delV = 1*circuit. This is in netlist format.* voltage sources:* Vname pos_terminal neg_terminal dc_val AC ac_valvdd vdd gnd vddvcm cm gnd 1.2Vvin1 in1 cm ac 'delV/2'vin2 cm in2 ac 'delV/2'* current sources:* Iname pos_terminal neg_terminal dc_valiss ss gnd 200u* a resistor:* Rname term1 term2 res_valRout ss gnd rout* a capacitor:* Cname term1 term2 cap_valCload out gnd 'cload'* a transistor:* Mname drain gate source bulk model_name W=width L=length* L=Ldrawn!.param wn = 25u+ wp = 10u+ l = 0.5umn1 load in1 ss gnd nmos w=wn l=l+ as='wn*3*l' ad='wn*3*l' ps='2*(wn+3*l)' pd='2*(wn+3*l)'mn2 out in2 ss gnd nmos w=wn l=l+ as='wn*3*l' ad='wn*3*l' ps='2*(wn+3*l)' pd='2*(wn+3*l)'mp1 load load vdd vdd pmos w=wp l=l+ as='wp*3*l' ad='wp*3*l' ps='2*(wp+3*l)' pd='2*(wp+3*l)'mp2 out load vdd vdd pmos w=wp l=l+ as='wp*3*l' ad='wp*3*l' ps='2*(wp+3*l)' pd='2*(wp+3*l)'* Simulation* DC sweep from .7V to 1.5V in .01V steps.dc vcm 0.7 1.5 0.1* AC sweep 10steps/decade from 1Hz to 1GHz varying* the output resistor from 10k to 30k in 5 evenly space steps..AC dec 10 10k 10G sweep rout lin 5 10k 30k* output results* some notes:* when doing DC sweeps, refer to* voltages at nodes by v(nodename)* currents in voltage sources by i(voltage_source)* when doing AC sweeps, refer to* voltage(mag) by vm(nodename)* voltage(phase) by vp(nodename)* voltage(magnitude in db) by vdb(nodename)* print statements list all the values you want to see..print DC v(out) i(vdd).print AC vm(out).measure dc gate_vol when i(vdd)=-0.5m.measure dc drain_vol find v(out) when i(vdd)=-0.5m.measure ac ugbw_frequency when vdb(out)=0.measure ac ugbw_phase find vp(out) when vdb(out)=0.measure ac ugbw_phase_margin param='180 + ugbw_phase'*.alter statements allow you to change a parameter and*then rerun all of the above simulations*syntax : .alter title.alter wn100.param wn = 100u+ wp = 25u.alter wn200.param wn = 200u+ wp = 50u*remember to end the file with .end AND a carriage