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Prelab 4 - FM Demodulation - EE133 - Prof. Dutton - Winter 2004 1EE133 - Prelab 4FM Demodu lation1 IntroductionFrom a very high le vel, we can describe the operation of the PLL as simply the inverse of the VCO operation.So, whereas the VCO outputs a signal whose frequency varies as a function of the input voltag e , the PLLoutputs a voltage whose size varies as a function of the input signal frequency. After Lab 2, you should havea sense of how the VCO is able to perform its function (if not, pleas e review the handouts on VCO’s - thiswill be important to understanding the P LL). Now, let’s look at how the PLL is implemented...Please refer to Figure 2 in the course of this discussion. At the heart of the PLL is a VCO. In fact,the VCO is nearly identical to the LM5 66 which you used in Lab 2 (I told you it would be important). Therest of the PLL is nothing more than a feedback loop placed around the VCO so that it can be automaticallyadjusted to replicate the frequency of the incoming signal.The feedback loop is straightforward as well. The first element (moving left to right in the diagra m) isa phase comparator. Essentially, this is just a multiplier (and is in fact represented by the multiplier s ymbolin the dia gram) which takes as its inputs the incoming signal and the output of the VCO. Assume for themoment that each sig nal is a square wave of a single frequency, but that the frequencies of the two are notthe same. Then, when they are multiplied together, the result is a train of pulses whose widths vary in timeas a function of the frequency offset between the two signals.Integrating this pulse train, which is the jo b of the low-pass filter that follows the phase comparator, yie ldsa slowly varying s ignal whose amplitude at any instant in time is proportional to the width of the pulsesat that time and (by transitivity) to the fr e quency difference between the signals. This signal, gained upby an a mount A, is then used to adjust the VCO output until the VCO and input signal are at the samefrequency. At that point, there will be a constant phase difference b e tween the two, yielding a constant DCvoltage from the integrator that ’locks’ the VCO at the correct frequency.Note tha t the input voltage which ’locks’ the VCO is actually the output of the PLL - it is a voltagewhose amplitude is proportional to the frequency of the input! Now, if the input is not at a single frequency,but instead is FM modulated so that its frequency changes in time according to some modulating signal,then the PLL output voltage will be changing in proportion to that frequency variation and will thereforeresemble the modulating signal - Presto, FM demodulation!TransmitterReceiverBNC toANTMixer(SA602)XOAudioAmpVCO(LM566)PowerAmpTank/ColpittsOscMixer(SA602)IFAmpLNABNC toANTBNC toSpeakerXOPLL(LM565)Figure 1: Roadmap for Lab 4Prelab 4 - FM Demodulation - EE133 - Prof. Dutton - Winter 2004 22 The Ph ase-Locked LoopTo provide you with a feel for the operation of the phase locked loop, you will simulate the phase lockedloop using the SPICE deck tha t has been provided on the server. The deck is a behavior model of the PLLfound in the HSPICE manuals. You are expected to test the model with the various different input signalsthat have been commented out in the SPICE deck. These inputs are:• A sinusoid at the free running frequency of the VCO (fmod= fV CO)• A sinusoid gre ater than the free running frequency of the VCO (fmod> fV C O)• A sinusoid less than the fr e e running frequency of the VCO (fmod< fV CO)For the three input signals at 1MHz, 0.99MHz and 1.01MHz, do the following:1. Using the Spice deck from the web, plot the transient output that appears on vcontrol, the o utputvoltage, and record its final DC value.2. For each of the three locked conditions, plot the input signal, vin, and the signal from the output ofthe VCO vvc o, on the same page. Change the x-axis so that you are only look ing at the signal from195us to 200us. This will allow to get past the startup trans ient, and will also allow you to see greaterdetail.3. C omment on the fina l DC voltage of the o utput for e ach of the three input signals. Do they agree withthe expected results?4. C omment on the phase difference between the input signal and the VCO output fo r each of the threeinputs. Are they what you would expect?3 FM Demodulation using the PLLIf a FM signal is fed as input to a PLL, the output voltage of the PLL will vary according to the frequencyvariations in the FM signal. But the instantaneous frequency of an FM signal varies according to thevoltage of the modulating signal. As a r e sult, the output vo ltage of the PLL becomes a scaled version of themodulating signal. What we have achieved therefore, is demodulation of the FM s ignal.1. Using the SPICE deck, change the input to the FM input and plot the transient on vcontrol, the outputvoltage of the PLL for a FM input. Be sure to change the trans ient time in the .tran statement. Yoursimula tion should take about 5 to 10 minutes. What is the fre quency of the output obtained? Is it thesame as the frequency of the waveform encoded in the FM input signal?2. C alculate the tota l harmonic distortion of the demodulated signal.4 Using A Practical PLL: the LM565To use the LM565 for FM demodulation, we set the free- running frequency of the PLL to be equal to thecarrier frequency of the FM signal so that frequency variations (modulation) of the input signal will notexceed the loop lo ck range. Pins 4 and 5 should be joined for our purposes. The demodulated signal isobtained from pin 7 through a coupling capacitor to remove any DC offset.From the LM565 datashee t, you ca n find that the fre e running frequency of the LM565 can be se t bythe timing resistors and capacitors, as well as many other useful pieces of information on the 565.1. Read the LM565 datasheet.2. Using a timing capacitor of 100pF and supply vo ltage of 9V, choose a value for the timing resistorrequired for a free-running frequency of 300kHz.Prelab 4 - FM Demodulation - EE133 - Prof. Dutton - Winter 2004 33. C ompute the hold range for our P LL? Is this sufficient for our ∆f = 50kHz from Lab 3?4. Wha t is the “Loop Gain” (KDKO) for your design? We desire the “Loop Bandwidth” to be greaterthan 100 kHz, so we will place a 330pF capacitor from pin 7 to Vccto act as a Lag Compensator (ifyou remember control theory). Verify that this is the correct choice for C.5. Build the circuit in


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Stanford EE 133 - FM Demodulation

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