RISC processorsCOMP375 1RISC ProcessorsCOMP375 Computer Architecture and Organizationblue slides ©Intel Gautam DoshiRISC Traits• Pipelined• Simple instructions• Few instructions• No microcode• Few addressing modes• Load/Store architecture• Sliding register stack• Delayed branches•FastCurrent RISC Systems• PowerPC – The processor in the Apple Power Mac. Produced by IBM and Apple.• Sparc – The processor in Sun workstations and servers. Produced by Sun Microsystems. First commercial RISC.• Itanium – In new servers replacing the Intel Pentium. Produced by Intel.Intel Itanium®• Intel’s latest RISC system.• The current processor is the Itanium 2.• Intel seems to indicate that this is the replacement for the Pentium chip.Support of Pentium Instructions• The Itanium can execute both Itanium instructions and Pentium (IA-32) instructions• There are jump to IA-32/Itanium instructionsRISC processorsCOMP375 2Instruction Bundles• Explicitly Parallel /instruction Computing (EPICEPIC)• Three 41 bit instructions are grouped into a bundle with a 5 bit template.• There must be no dependencies within the instructions of a bundle.Compiler to Processor Hints• Every memory load and store in the Itanium architecture has a 2-bit cache hint field• The compiler can provide a hint to indicate if a branch is likely to be taken.• Templates define which execution units will be used and if dependencies exist.RISC processorsCOMP375 3Register Stacks• Many RISC processors have a large number of registers, not all of which are visible at any one time.• The mapping of register X to a hardware register changes when a function is called.Before a Function Call• Assume the assembly language programmer sees 32 registers.• Before a function call, arguments and the return address are put in registers R24 to R31.R24 R31R16 R23R8 R15R0 R7After a Function Call• After a function call, the input arguments and the return address are available in registers R8 to R15.• R16 to R23 are used for local variables.• R24 to R31 contain arguments to next functionR24 R31R16 R23R8 R15R0 R7After another Function Call• After another function call, the input arguments and the return address are again available in registers R8 to R15.• Return values are also put in R8 to R15 upon function return.R24 R31R16 R23R8 R15R0 R7RISC processorsCOMP375 4After Function Return• After the function return, the return values are available in registers R24 to R31.R24 R31R16 R23R8 R15R0 R7Itanium Register Stack• The Itanium uses a sliding register system somewhat similar to the generic description• General registers 0 through 31 are termed the static general registers.• General registers 32 through 127 are termed the stacked general registers.• A function can specify how many of the stacked general registers the system is to shift.• GP0 is always zero.Itanium RegistersItanium Floating Point• The Itanium has 128 floating-point registers• Each register holds an 82-bit floating point value.• Values are rounded as they are stored as 32 bit floats or 64 bit doubles.RISC processorsCOMP375 5Endian• The Itanium can execute in Big Endian or Little Endian mode.• Instruction fetches are always Little EndianItanium OS Support• Redhat Linux servers will run on the Itanium. The desktop does not.• Microsoft Windows Servers will run on the Itanium. Windows XP Professional will not.• Sun Solaris runs on 64 bit Sparc processors, but not on the Intel Itanium.PowerPC RegistersPowerPC Branches• Every jump instruction has two extra bits• AA bit– 1 (use absolute address)– 0 (use relative address)•LK bit– 0 (no link --- branch)– 1 (link --- turns branch into a procedure